* C:\Users\User\Documents\LTspice\Conactor Based Low-side design.asc
* Generated by LTspice 24.1.9 for Windows.
M1 PFET_bridge PCHG 0 0 BSP89
D1 N005 N003 MMSD4148
R1 5V N005 10k
V1 N001 0 57
V2 3V3 0 3.3
R2 N003 To_MCU_2 1Meg
D2 0 To_MCU_2 3V3Zener
R3 N003 PFET_bridge 25
D3 0 PFET_bridge D
V3 NC_01 0 PULSE(0 5 0 0.1 0.1 1 2 4)
V4 N006 0 5
D6 N004 P001 BAT54
R5 P001 N008 10Meg
R6 0 N008 500k
D7 0 N008 EDZV6_8B
M4 N012 N008 0 0 NMOS
R7 N012 To_MCU_3 1k
R8 To_MCU_3 3V3 1Meg
V7 5V 0 5
D5 N009 N004 MMSD4148
R9 3V3 N009 10k
D4 N004 N003 D
R4 N001 NC_02 10 pwr=1000
M2 N007 To_MCU_2 0 0 BSP89
R11 3V3 N007 10k
M3 N004 DCHG 0 0 NMOS
M5 N010 N011 0 0 BSP89
R10 3V3 N010 10k
R12 N011 PFET_bridge 10k
D8 0 N011 BZX84C15L
.model D D
.lib C:\Users\User\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\Users\User\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 10
.model 3V3Zener D(Ron=0 Roff=100Meg Vfwd=0.7 Vrev 3.3)
* LOAD DETECT
* PCHG FET DET
* THERMAL FUSE DET
* Contactor Weld DET
* Bat+
* Bat-
* Pack-
* Load
.model zeeno D(Ron=0 Roff=1Meg Vfwd=0.7 Vrev 3.3)
.backanno
.end