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feat: reject 0x500 to 0x600 CAN id

stable
@rakshita4 2024-11-12 16:54:07 +05:30
parent b345c3ae48
commit 3d3b39960e
4 changed files with 413 additions and 137 deletions
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@ -2,116 +2,79 @@
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@ -481,6 +444,247 @@
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51
Core/Source/ivec_mcal_mcan.c
View File

@ -26,6 +26,7 @@ volatile uint8_t u8CallBack_buff[8]={0};
volatile IVEC_McalStatus_e l_statusFlag = IVEC_MCAL_STATUS_SUCCESS;
extern volatile uint8_t u8CANDataAct;
/*REQUIRED MCAN CONFIGS*/
#define MCAN_FILTER_SIZE 2u
__attribute__((weak)) void mcu_FDCAN_RxFifo_Callback(uint32_t Identifier, uint8_t *data, uint16_t DataLength)
@ -71,20 +72,20 @@ static DL_MCAN_ConfigParams gMCAN0ConfigParams={
.timeoutCntEnable = false,
.filterConfig.rrfs = false,
.filterConfig.rrfe = false,
.filterConfig.anfe = 0,
.filterConfig.anfs = 0,
.filterConfig.anfe = 3,
.filterConfig.anfs = 3,
};
static DL_MCAN_MsgRAMConfigParams gMCAN0MsgRAMConfigParams ={
/* Standard ID Filter List Start Address. */
.flssa = 0 ,
.flssa = 1,
/* List Size: Standard ID. */
.lss = 0 ,
.lss = MCAN_FILTER_SIZE,
/* Extended ID Filter List Start Address. */
.flesa = 0 ,
.flesa = 48 ,
/* List Size: Extended ID. */
.lse = 0 ,
.lse = 2 ,
/* Tx Buffers Start Address. */
.txStartAddr = 10 ,
/* Number of Dedicated Transmit Buffers. */
@ -100,16 +101,16 @@ static DL_MCAN_MsgRAMConfigParams gMCAN0MsgRAMConfigParams ={
/* Level for Tx Event FIFO watermark interrupt. */
.txEventFIFOWaterMark = 0,
/* Rx FIFO0 Start Address. */
.rxFIFO0startAddr = 172 ,
.rxFIFO0startAddr = 170 ,
/* Number of Rx FIFO elements. */
.rxFIFO0size = 64 ,
.rxFIFO0size = 10 ,
/* Rx FIFO0 Watermark. */
.rxFIFO0waterMark = 0,
.rxFIFO0OpMode = 0,
/* Rx FIFO1 Start Address. */
.rxFIFO1startAddr = 192 ,
.rxFIFO1startAddr = 190 ,
/* Number of Rx FIFO elements. */
.rxFIFO1size = 64 ,
.rxFIFO1size = 10 ,
/* Level for Rx FIFO 1 watermark interrupt. */
.rxFIFO1waterMark = 10,
/* FIFO blocking mode. */
@ -124,6 +125,7 @@ static DL_MCAN_MsgRAMConfigParams gMCAN0MsgRAMConfigParams ={
.rxFIFO1ElemSize = DL_MCAN_ELEM_SIZE_8BYTES,
};
static DL_MCAN_BitTimingParams gMCAN0BitTimes_500 = {
/* Arbitration Baud Rate Pre-scaler. */
.nomRatePrescalar = 0,
@ -164,17 +166,17 @@ static DL_MCAN_BitTimingParams gMCAN0BitTimes_250 = {
static const DL_MCAN_StdMsgIDFilterElement gMCAN0StdFiltelem1 = {
.sfec = 0x1,
.sft = 0x01,
.sfid1 = 0x1AE,
.sfid2 = 0x520,
.sfec = 001,
.sft = 0x00,
.sfid1 = 0,
.sfid2 = 1280,
};
static const DL_MCAN_StdMsgIDFilterElement gMCAN0StdFiltelem2 = {
.sfec = 0x1,
.sft = 0x00,
.sfid1 = 0xBB,
.sfid2 = 0xBB,
.sfid1 = 1536,
.sfid2 = 2046,
};
static const DL_MCAN_StdMsgIDFilterElement gMCAN0StdFiltelem3 = {
@ -201,15 +203,16 @@ static const DL_MCAN_StdMsgIDFilterElement gMCAN0StdFiltelem5 = {
static const DL_MCAN_ExtMsgIDFilterElement gMCAN0ExtFiltelem1 = {
.efec = 0x1,
.eft = 0x0,
.efid1 = 0x18904001,
.efid2 = 0x18904001,
.efid1 = 2047,
.efid2 = 33554431,
};
static const DL_MCAN_ExtMsgIDFilterElement gMCAN0ExtFiltelem2 = {
.efec = 0x1,
.eft = 0x0,
.efid1 = 0x1CECFF23,
.efid2 = 0x1CECFF23,
.efid1 = 2047,
.efid2 = 33554431,
};
static const DL_MCAN_ExtMsgIDFilterElement gMCAN0ExtFiltelem3 = {
@ -385,9 +388,9 @@ IVEC_McalStatus_e xMCAL_MCANInit(MCAN_Regs* MCAN, xCAN_baud_t BAUD)
DL_MCAN_msgRAMConfig(MCAN, (DL_MCAN_MsgRAMConfigParams*) &gMCAN0MsgRAMConfigParams);
/* Configure Standard ID filter element */
// DL_MCAN_addStdMsgIDFilter(MCAN, 0U, (DL_MCAN_StdMsgIDFilterElement *) &gMCAN0StdFiltelem1);
DL_MCAN_addStdMsgIDFilter(MCAN, 0U, (DL_MCAN_StdMsgIDFilterElement *) &gMCAN0StdFiltelem1);
//
// DL_MCAN_addStdMsgIDFilter(MCAN, 1U, (DL_MCAN_StdMsgIDFilterElement *) &gMCAN0StdFiltelem2);
DL_MCAN_addStdMsgIDFilter(MCAN, 1U, (DL_MCAN_StdMsgIDFilterElement *) &gMCAN0StdFiltelem2);
//
// DL_MCAN_addStdMsgIDFilter(MCAN, 2U, (DL_MCAN_StdMsgIDFilterElement *) &gMCAN0StdFiltelem3);
//
@ -395,9 +398,9 @@ IVEC_McalStatus_e xMCAL_MCANInit(MCAN_Regs* MCAN, xCAN_baud_t BAUD)
//
// DL_MCAN_addStdMsgIDFilter(MCAN, 4U, (DL_MCAN_StdMsgIDFilterElement *) &gMCAN0StdFiltelem5);
//
// DL_MCAN_addExtMsgIDFilter(MCAN, 0U,(DL_MCAN_ExtMsgIDFilterElement *)&gMCAN0ExtFiltelem1);
//DL_MCAN_addExtMsgIDFilter(MCAN, 0U,(DL_MCAN_ExtMsgIDFilterElement *)&gMCAN0ExtFiltelem1);
//
// DL_MCAN_addExtMsgIDFilter(MCAN, 1U,(DL_MCAN_ExtMsgIDFilterElement *)&gMCAN0ExtFiltelem2);
DL_MCAN_addExtMsgIDFilter(MCAN, 1U,(DL_MCAN_ExtMsgIDFilterElement *)&gMCAN0ExtFiltelem2);
//
// DL_MCAN_addExtMsgIDFilter(MCAN, 2U,(DL_MCAN_ExtMsgIDFilterElement *)&gMCAN0ExtFiltelem3);

4
mspm0g3507.lds
View File

@ -7,7 +7,7 @@ _Min_Stack_Size = 0x000012E8; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
FLASH (RX) : ORIGIN = 0x00008000, LENGTH = 0x00018000
FLASH (RX) : ORIGIN = 0x00000000, LENGTH = 0x00020000
SRAM (RWX) : ORIGIN = 0x20200000, LENGTH = 0x00008000
BCR_CONFIG (R) : ORIGIN = 0x41C00000, LENGTH = 0x00000080
BSL_CONFIG (R) : ORIGIN = 0x41C00100, LENGTH = 0x00000080
@ -33,7 +33,7 @@ SECTIONS
{
/* section for the interrupt vector area */
PROVIDE (_intvecs_base_address =
DEFINED(_intvecs_base_address) ? _intvecs_base_address : 0x00008000);
DEFINED(_intvecs_base_address) ? _intvecs_base_address : 0x00000000);
.intvecs (_intvecs_base_address) : AT (_intvecs_base_address) {
KEEP (*(.intvecs))