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chg-stn-motherboard-ti-mcu
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fix: all ids are being replaced by abcdef

stable
Gurpal singh 2025-03-17 11:45:53 +05:30
parent e3bdc83387
commit 892b038c1f
2 changed files with 14 additions and 11 deletions
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21
ivec_RTE/src/ivec_rte.c
View File

@ -478,17 +478,17 @@ void vCcUartRxToCanTx(IVEC_EcuCommonCanFrame_s* pxCanMsg)
{
if(pxCanMsg->u32CanId != 0x00)
{
if(pxCanMsg->u32CanId == 0xabcdef)
{
pxCanMsg->u32CanId = g_u32CanId;
xECU_WriteDataOverCAN(&g_xCanHandle, &pxCanMsg->pucCanData[0], pxCanMsg->u32CanId, pxCanMsg->ucCanDlc, 0);
}
else if (pxCanMsg->u32CanId == 0x1cea6969)
if (pxCanMsg->u32CanId == 0x1cea6969)
{
iECU_UartInitiateTransmit(&g_xUartHandle, (uint32_t)pxCanMsg->u32CanId,(uint8_t*)&pxCanMsg->pucCanData[0],(uint8_t)pxCanMsg->ucCanDlc);
}
else
{
if(pxCanMsg->u32CanId == 0xabcdef)
{
pxCanMsg->u32CanId = g_u32CanId;
}
xECU_WriteDataOverCAN(&g_xCanHandle, &pxCanMsg->pucCanData[0], pxCanMsg->u32CanId, pxCanMsg->ucCanDlc, 0);
}
}
@ -533,7 +533,7 @@ void vRTE_CcUartRxProcess(void)
if (l_ucFrameStart == NULL)
{
// __prv_i32BfrIdx = 0;
__prv_i32BfrIdx = 0;
break;
}
if (l_ucFrameEnd == NULL)
@ -709,11 +709,14 @@ void vRTE_ProcessCanData(void)
int l_i32RetSize = 0;
uint8_t l_u8UartBuffer[30] = { 0 };
int l_i32Status = -1;
l_i32RetSize = u16CMPLX_vFrameEncode((uint32_t)l_xCanBuff.u32UlId, (uint8_t*)&l_xCanBuff.u8Data[0], (int32_t)l_xCanBuff.u8Length, l_u8UartBuffer, 30);
if(l_xCanBuff.u32UlId == g_u32CanId)
{
l_xCanBuff.u32UlId = 0xabcdef;
l_i32RetSize = u16CMPLX_vFrameEncode((uint32_t)0xabcdef, (uint8_t*)&l_xCanBuff.u8Data[0], (int32_t)l_xCanBuff.u8Length, l_u8UartBuffer, 30);
}
l_i32RetSize = u16CMPLX_vFrameEncode((uint32_t)l_xCanBuff.u32UlId, (uint8_t*)&l_xCanBuff.u8Data[0], (int32_t)l_xCanBuff.u8Length, l_u8UartBuffer, 30);
l_i32Status = IVEC_ECUUartWrite(&__gprv_UartCcHandle, l_u8UartBuffer, l_i32RetSize);
#endif

4
mspm0g3507.lds
View File

@ -7,7 +7,7 @@ _Min_Stack_Size = 0x000012E8; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
FLASH (RX) : ORIGIN = 0x00000000, LENGTH = 0x00020000
FLASH (RX) : ORIGIN = 0x00008000, LENGTH = 0x00018000
SRAM (RWX) : ORIGIN = 0x20200000, LENGTH = 0x00008000
BCR_CONFIG (R) : ORIGIN = 0x41C00000, LENGTH = 0x00000080
BSL_CONFIG (R) : ORIGIN = 0x41C00100, LENGTH = 0x00000080
@ -33,7 +33,7 @@ SECTIONS
{
/* section for the interrupt vector area */
PROVIDE (_intvecs_base_address =
DEFINED(_intvecs_base_address) ? _intvecs_base_address : 0x00000000);
DEFINED(_intvecs_base_address) ? _intvecs_base_address : 0x00008000);
.intvecs (_intvecs_base_address) : AT (_intvecs_base_address) {
KEEP (*(.intvecs))