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chg-stn-motherboard-ti-mcu
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refactor: Removed bootloader addresses, UART debug messages, and unused relay pin initialization

stable
Rakshita 2025-01-02 17:53:24 +05:30
parent 8faece3cee
commit 9f0e5a215d
5 changed files with 27 additions and 222 deletions
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64
Generated Codes/ti_msp_dl_config.c
View File

@ -111,7 +111,7 @@ SYSCONFIG_WEAK void SYSCFG_DL_initPower(void)
DL_MCAN_reset(MCAN0_INST);
DL_GPIO_enablePower(GPIOA);
DL_GPIO_enablePower(GPIOB);
DL_GPIO_enablePower(GPIOB);
#if UART_PIN_SELECTION == 1
DL_UART_Main_reset(UART2);
@ -122,60 +122,10 @@ SYSCONFIG_WEAK void SYSCFG_DL_initPower(void)
DL_UART_Main_enablePower(UART1);
#elif UART_PIN_SELECTION == 3
// UART1 pins
DL_UART_Main_reset(UART1);
DL_UART_Main_enablePower(UART1);
// DL_UART_Main_reset(UART2);
// DL_UART_Main_enablePower(UART2);
DL_GPIO_initDigitalOutput(IOMUX_PINCM48);
DL_GPIO_initDigitalOutput(IOMUX_PINCM45);
DL_GPIO_initDigitalOutput(IOMUX_PINCM44);
DL_GPIO_initDigitalOutput(IOMUX_PINCM43);
DL_GPIO_initDigitalOutput(IOMUX_PINCM33);
DL_GPIO_initDigitalOutput(IOMUX_PINCM32);
DL_GPIO_initDigitalOutput(IOMUX_PINCM31);
DL_GPIO_initDigitalOutput(IOMUX_PINCM26);
DL_GPIO_initDigitalOutput(IOMUX_PINCM25);
DL_GPIO_initDigitalOutput(IOMUX_PINCM54);
DL_GPIO_initDigitalOutput(IOMUX_PINCM52);
DL_GPIO_clearPins(GPIOA, GPIO_relay_pin_fan_2_relay_PIN);
//
DL_GPIO_enableOutput(GPIOA, GPIO_relay_pin_fan_2_relay_PIN);
DL_GPIO_clearPins(GPIOB, GPIO_relay_pin_relay_1_PIN |
GPIO_relay_pin_relay_2_PIN |
GPIO_relay_pin_relay_3_PIN |
GPIO_relay_pin_relay_4_PIN |
GPIO_relay_pin_relay_5_PIN |
GPIO_relay_pin_relay_6_PIN |
GPIO_relay_pin_relay_7_PIN |
GPIO_relay_pin_relay_8_PIN |
GPIO_relay_pin_relay_9_PIN |
GPIO_relay_pin_fan_1_relay_PIN);
DL_GPIO_enableOutput(GPIOB, GPIO_relay_pin_relay_1_PIN |
GPIO_relay_pin_relay_2_PIN |
GPIO_relay_pin_relay_3_PIN |
GPIO_relay_pin_relay_4_PIN |
GPIO_relay_pin_relay_5_PIN |
GPIO_relay_pin_relay_6_PIN |
GPIO_relay_pin_relay_7_PIN |
GPIO_relay_pin_relay_8_PIN |
GPIO_relay_pin_relay_9_PIN |
GPIO_relay_pin_fan_1_relay_PIN);
DL_UART_Main_reset(UART2);
DL_UART_Main_enablePower(UART2);
#endif
@ -197,10 +147,10 @@ SYSCONFIG_WEAK void SYSCFG_DL_GPIO_init(void)
DL_GPIO_initPeripheralInputFunction(GPIO_CAPTURE_0_C0_IOMUX,GPIO_CAPTURE_0_C0_IOMUX_FUNC);
// DL_GPIO_initPeripheralOutputFunction(
// GPIO_UART_0_IOMUX_TX, GPIO_UART_0_IOMUX_TX_FUNC);
// DL_GPIO_initPeripheralInputFunction(
// GPIO_UART_0_IOMUX_RX, GPIO_UART_0_IOMUX_RX_FUNC);
DL_GPIO_initPeripheralOutputFunction(
GPIO_UART_0_IOMUX_TX, GPIO_UART_0_IOMUX_TX_FUNC);
DL_GPIO_initPeripheralInputFunction(
GPIO_UART_0_IOMUX_RX, GPIO_UART_0_IOMUX_RX_FUNC);
DL_GPIO_initDigitalInputFeatures(GPIO_GRP_0_PIN_0_IOMUX,
DL_GPIO_INVERSION_DISABLE, DL_GPIO_RESISTOR_NONE,

55
Generated Codes/ti_msp_dl_config.h
View File

@ -67,29 +67,6 @@ extern "C" {
* MSP DL.
*/
/* Defines for relay_1: GPIOB.20 with pinCMx 48 on package pin 19 */
#define GPIO_relay_pin_relay_1_PIN (DL_GPIO_PIN_20)
/* Defines for relay_2: GPIOB.19 with pinCMx 45 on package pin 16 */
#define GPIO_relay_pin_relay_2_PIN (DL_GPIO_PIN_19)
/* Defines for relay_3: GPIOB.18 with pinCMx 44 on package pin 15 */
#define GPIO_relay_pin_relay_3_PIN (DL_GPIO_PIN_18)
/* Defines for relay_4: GPIOB.17 with pinCMx 43 on package pin 14 */
#define GPIO_relay_pin_relay_4_PIN (DL_GPIO_PIN_17)
/* Defines for relay_5: GPIOB.16 with pinCMx 33 on package pin 4 */
#define GPIO_relay_pin_relay_5_PIN (DL_GPIO_PIN_16)
/* Defines for relay_6: GPIOB.15 with pinCMx 32 on package pin 3 */
#define GPIO_relay_pin_relay_6_PIN (DL_GPIO_PIN_15)
/* Defines for relay_7: GPIOB.14 with pinCMx 31 on package pin 2 */
#define GPIO_relay_pin_relay_7_PIN (DL_GPIO_PIN_14)
/* Defines for relay_8: GPIOB.9 with pinCMx 26 on package pin 61 */
#define GPIO_relay_pin_relay_8_PIN (DL_GPIO_PIN_9)
/* Defines for relay_9: GPIOB.8 with pinCMx 25 on package pin 60 */
#define GPIO_relay_pin_relay_9_PIN (DL_GPIO_PIN_8)
/* Defines for fan_1_relay: GPIOB.24 with pinCMx 52 on package pin 23 */
#define GPIO_relay_pin_fan_1_relay_PIN (DL_GPIO_PIN_24)
/* Defines for fan_2_relay: GPIOA.24 with pinCMx 54 on package pin 25 */
#define GPIO_relay_pin_fan_2_relay_PIN (DL_GPIO_PIN_24)
/* clang-format off */
#define POWER_STARTUP_DELAY (16)
@ -132,22 +109,22 @@ extern "C" {
///* Defines for UART_0 */
//#define UART_0_INST UART2
//#define UART_0_INST_FREQUENCY 24000000
//#define UART_0_INST_IRQHandler UART2_IRQHandler
//#define UART_0_INST_INT_IRQN UART2_INT_IRQn
//#define GPIO_UART_0_RX_PORT GPIOB
//#define GPIO_UART_0_TX_PORT GPIOB
//#define GPIO_UART_0_RX_PIN DL_GPIO_PIN_16
//#define GPIO_UART_0_TX_PIN DL_GPIO_PIN_15
//#define GPIO_UART_0_IOMUX_RX (IOMUX_PINCM33)
//#define GPIO_UART_0_IOMUX_TX (IOMUX_PINCM32)
//#define GPIO_UART_0_IOMUX_RX_FUNC IOMUX_PINCM33_PF_UART2_RX
//#define GPIO_UART_0_IOMUX_TX_FUNC IOMUX_PINCM32_PF_UART2_TX
//#define UART_0_BAUD_RATE (115200)
//#define UART_0_IBRD_24_MHZ_115200_BAUD (13)
//#define UART_0_FBRD_24_MHZ_115200_BAUD (1)
/* Defines for UART_0 */
#define UART_0_INST UART2
#define UART_0_INST_FREQUENCY 24000000
#define UART_0_INST_IRQHandler UART2_IRQHandler
#define UART_0_INST_INT_IRQN UART2_INT_IRQn
#define GPIO_UART_0_RX_PORT GPIOB
#define GPIO_UART_0_TX_PORT GPIOB
#define GPIO_UART_0_RX_PIN DL_GPIO_PIN_16
#define GPIO_UART_0_TX_PIN DL_GPIO_PIN_15
#define GPIO_UART_0_IOMUX_RX (IOMUX_PINCM33)
#define GPIO_UART_0_IOMUX_TX (IOMUX_PINCM32)
#define GPIO_UART_0_IOMUX_RX_FUNC IOMUX_PINCM33_PF_UART2_RX
#define GPIO_UART_0_IOMUX_TX_FUNC IOMUX_PINCM32_PF_UART2_TX
#define UART_0_BAUD_RATE (115200)
#define UART_0_IBRD_24_MHZ_115200_BAUD (13)
#define UART_0_FBRD_24_MHZ_115200_BAUD (1)

2
ivec_ECU/ivec_ecu_can/src/ivec_ecu_can.c
View File

@ -113,7 +113,5 @@ IVEC_EcuCommonErr_e xECU_GetCanStatus(MCAN_Regs* MCAN, uint16_t speed)
if( xMCAL_getMCAN_ErrorStatus(&l_ucErrorString) == IVEC_MCAL_STATUS_ERROR )
{
xECU_CanReInit(MCAN, speed);
return commonECU_FAIL;
}
return commonECU_SUCCESS;
}

124
ivec_RTE/src/ivec_rte.c
View File

@ -255,7 +255,6 @@ void vCanFilterSaveVal(uint8_t ucIdx, uint32_t Filter, bool isExtended)
}
void vCanFilterReset() {
uint32_t i;
@ -429,11 +428,8 @@ void vRTE_UARTDataProcess(void)
}
if ( retCode >= 0 && (ulId > 0x00 && ulId < 0xffffffff) )
{
uint8_t status;
//__gprv_u8Buf = (__gprv_u8Buf + 1) % 2;
status = xECU_WriteDataOverCAN(&g_pu8Buf[PKT_HEADER], ulId, retCode, 0);
if(status != 0)
vECU_InitiateUartToCanTransmit(&g_xUartHandle, 0x5, g_pu8Buf, 0);
xECU_WriteDataOverCAN(&g_pu8Buf[PKT_HEADER], ulId, retCode, 0);
}
}
@ -445,19 +441,6 @@ void vRTE_CANDataProcess(void)
volatile uint8_t l_u8TxBurstMessages = 0;
while( xECU_CANGetData(&xBuff) == commonECU_SUCCESS )
{
#if UART_PIN_SELECTION == 3
if(xBuff.id == 0x6fe69)
{
uint16_t relay_status = (xBuff.data[0] << 8) |xBuff.data[1];
control_relays(relay_status); // Control relays based on the relay_status
}
// if(xBuff.id == 0x6ff69)
// {
// control_relays(&xBuff);
// }
#endif
if( (xBuff.id == 0x16) && (xBuff.data[0] = 'V') && \
(xBuff.data[1] == 'E') && (xBuff.data[2] == 'C'))
{
@ -473,109 +456,6 @@ void vRTE_CANDataProcess(void)
else
break;
}
uint8_t status;
status = xECU_GetCanStatus(CANFD0, g_u16CanSpeed);
if ( status != 0)
vECU_InitiateUartToCanTransmit(&g_xUartHandle, 0x4, g_pu8Buf, 0);
xECU_GetCanStatus(CANFD0, g_u16CanSpeed);
}
// Function to control individual relays based on relay_status (16 bits)
void control_relays(uint16_t relay_status)
{
//we'll use the 9-bit status to control the relays, where the least significant bit corresponds to Relay 1 and the most significant bit corresponds to Relay 9.
// Clear all relays first (set all relay pins to LOW)
DL_GPIO_clearPins(GPIOB, GPIO_relay_pin_relay_1_PIN |
GPIO_relay_pin_relay_2_PIN |
GPIO_relay_pin_relay_3_PIN |
GPIO_relay_pin_relay_4_PIN |
GPIO_relay_pin_relay_5_PIN |
GPIO_relay_pin_relay_6_PIN |
GPIO_relay_pin_relay_7_PIN |
GPIO_relay_pin_relay_8_PIN |
GPIO_relay_pin_relay_9_PIN |
GPIO_relay_pin_fan_1_relay_PIN);
DL_GPIO_clearPins(GPIOA, GPIO_relay_pin_fan_2_relay_PIN);
// Check each bit of relay_status and set the corresponding relay pin
if ((relay_status & 0x01) != 0) { // Bit 0: Relay 1
DL_GPIO_setPins(GPIOB, GPIO_relay_pin_relay_9_PIN);
}
if ((relay_status & 0x02) != 0) { // Bit 1: Relay 2
DL_GPIO_setPins(GPIOB, GPIO_relay_pin_relay_8_PIN);
}
if ((relay_status & 0x04) != 0) { // Bit 2: Relay 3
DL_GPIO_setPins(GPIOB, GPIO_relay_pin_relay_7_PIN);
}
if ((relay_status & 0x08) != 0) { // Bit 3: Relay 4
DL_GPIO_setPins(GPIOB, GPIO_relay_pin_relay_6_PIN);
}
if ((relay_status & 0x10) != 0) { // Bit 4: Relay 5
DL_GPIO_setPins(GPIOB, GPIO_relay_pin_relay_5_PIN);
}
if ((relay_status & 0x20) != 0) { // Bit 5: Relay 6
DL_GPIO_setPins(GPIOB, GPIO_relay_pin_relay_4_PIN);
}
if ((relay_status & 0x40) != 0) { // Bit 6: Relay 7
DL_GPIO_setPins(GPIOB, GPIO_relay_pin_relay_3_PIN);
}
if ((relay_status & 0x80) != 0) { // Bit 7: Relay 8
DL_GPIO_setPins(GPIOB, GPIO_relay_pin_relay_2_PIN);
}
if ((relay_status & 0x100) != 0) { // Bit 8: Relay 9
DL_GPIO_setPins(GPIOB, GPIO_relay_pin_relay_1_PIN);
}
if ((relay_status & 0x200) != 0) { // Bit 9: fan 1 Relay 10
DL_GPIO_setPins(GPIOB, GPIO_relay_pin_fan_1_relay_PIN);
}
if ((relay_status & 0x400) != 0) { // Bit 10: fan 2 Relay 11
DL_GPIO_setPins(GPIOA, GPIO_relay_pin_fan_2_relay_PIN);
}
}
//// Function to control relays based on the payload
//void control_relays(const can_buff_t *buffer)
//{
// // Combine the two bytes to form a 16-bit value
// uint16_t relay_status = (buffer->data[0] << 8) | buffer->data[1];
//
// // Relay mask for GPIOB (for relays 1-9)
// uint32_t relay_mask = 0;
//
// //we'll use the 9-bit status to control the relays, where the least significant bit corresponds to Relay 1 and the most significant bit corresponds to Relay 9.
// // Iterate through the 9 bits to determine the status of each relay
// for (int i = 0; i < 9; i++) {
// uint8_t bit_status = (relay_status >> i) & 0x01; // Extract the ith bit
//
// if (bit_status == 1) {
// // Set the corresponding relay pin in the relay mask
// switch (i) {
// case 0: relay_mask |= GPIO_relay_pin_relay_1_PIN; break;
// case 1: relay_mask |= GPIO_relay_pin_relay_2_PIN; break;
// case 2: relay_mask |= GPIO_relay_pin_relay_3_PIN; break;
// case 3: relay_mask |= GPIO_relay_pin_relay_4_PIN; break;
// case 4: relay_mask |= GPIO_relay_pin_relay_5_PIN; break;
// case 5: relay_mask |= GPIO_relay_pin_relay_6_PIN; break;
// case 6: relay_mask |= GPIO_relay_pin_relay_7_PIN; break;
// case 7: relay_mask |= GPIO_relay_pin_relay_8_PIN; break;
// case 8: relay_mask |= GPIO_relay_pin_relay_9_PIN; break;
// }
// }
// }
//
// // First, clear all relays to ensure all relays are off
// DL_GPIO_clearPins(GPIOB, GPIO_relay_pin_relay_1_PIN |
// GPIO_relay_pin_relay_2_PIN |
// GPIO_relay_pin_relay_3_PIN |
// GPIO_relay_pin_relay_4_PIN |
// GPIO_relay_pin_relay_5_PIN |
// GPIO_relay_pin_relay_6_PIN |
// GPIO_relay_pin_relay_7_PIN |
// GPIO_relay_pin_relay_8_PIN |
// GPIO_relay_pin_relay_9_PIN);
//
// // Set the corresponding relays based on the relay_status
// DL_GPIO_setPins(GPIOB, relay_mask); // Turn ON selected relays in GPIOB
//}

4
mspm0g3507.lds
View File

@ -7,7 +7,7 @@ _Min_Stack_Size = 0x000012E8; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
FLASH (RX) : ORIGIN = 0x00008000, LENGTH = 0x00018000
FLASH (RX) : ORIGIN = 0x00000000, LENGTH = 0x00020000
SRAM (RWX) : ORIGIN = 0x20200000, LENGTH = 0x00008000
BCR_CONFIG (R) : ORIGIN = 0x41C00000, LENGTH = 0x00000080
BSL_CONFIG (R) : ORIGIN = 0x41C00100, LENGTH = 0x00000080
@ -33,7 +33,7 @@ SECTIONS
{
/* section for the interrupt vector area */
PROVIDE (_intvecs_base_address =
DEFINED(_intvecs_base_address) ? _intvecs_base_address : 0x00008000);
DEFINED(_intvecs_base_address) ? _intvecs_base_address : 0x00000000);
.intvecs (_intvecs_base_address) : AT (_intvecs_base_address) {
KEEP (*(.intvecs))