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feat: Update clock configuration for UART3

stable
Rakshita 2025-03-11 19:56:06 +05:30
parent 9d4bd991d5
commit e3bdc83387
2 changed files with 17 additions and 12 deletions
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10
Core/Source/ivec_mcal_uart.c
View File

@ -550,6 +550,7 @@ static IVEC_McalCommonErr_e __prv_McalUartInitInstance(IVEC_McalUartHandle_s* px
DL_UART_Main_enablePower(UART3); DL_UART_Main_enablePower(UART3);
DL_GPIO_initPeripheralOutputFunction(IOMUX_PINCM36, IOMUX_PINCM36_PF_UART3_TX); DL_GPIO_initPeripheralOutputFunction(IOMUX_PINCM36, IOMUX_PINCM36_PF_UART3_TX);
DL_GPIO_initPeripheralInputFunction(IOMUX_PINCM35, IOMUX_PINCM35_PF_UART3_RX); DL_GPIO_initPeripheralInputFunction(IOMUX_PINCM35, IOMUX_PINCM35_PF_UART3_RX);
} }
UART_Regs* pxUartInstance = __prv_McalGetUartInstance(pxUartHandle->eUartPortNumber); UART_Regs* pxUartInstance = __prv_McalGetUartInstance(pxUartHandle->eUartPortNumber);
@ -601,7 +602,14 @@ static IVEC_McalCommonErr_e __prv_McalUartInitInstance(IVEC_McalUartHandle_s* px
DL_UART_ClockConfig xUartClockConfig = { 0 }; DL_UART_ClockConfig xUartClockConfig = { 0 };
xUartClockConfig.clockSel = DL_UART_CLOCK_BUSCLK; xUartClockConfig.clockSel = DL_UART_CLOCK_BUSCLK;
xUartClockConfig.divideRatio = DL_UART_MAIN_CLOCK_DIVIDE_RATIO_1; if(pxUartHandle->eUartPortNumber == IVEC_MCAL_UART_PORT_4)
{
xUartClockConfig.divideRatio = DL_UART_MAIN_CLOCK_DIVIDE_RATIO_2;
}
else
{
xUartClockConfig.divideRatio = DL_UART_MAIN_CLOCK_DIVIDE_RATIO_1;
}
DL_UART_Main_setClockConfig(pxUartInstance, (DL_UART_Main_ClockConfig*) &xUartClockConfig); DL_UART_Main_setClockConfig(pxUartInstance, (DL_UART_Main_ClockConfig*) &xUartClockConfig);
DL_UART_Main_init(pxUartInstance, (DL_UART_Main_Config*) &xUartConfig); DL_UART_Main_init(pxUartInstance, (DL_UART_Main_Config*) &xUartConfig);

19
ivec_RTE/src/ivec_rte.c
View File

@ -665,6 +665,14 @@ void vRTE_ProcessUartData(void)
if ( l_eRetCode >= 0 && (l_u32Id > 0x00 && l_u32Id < 0xffffffff) ) if ( l_eRetCode >= 0 && (l_u32Id > 0x00 && l_u32Id < 0xffffffff) )
{ {
//_prvU8Buffer = (_prvU8Buffer + 1) % 2; //_prvU8Buffer = (_prvU8Buffer + 1) % 2;
if(l_u32Id == 0x1cecff69)
{
int l_i32RetSize = 0;
uint8_t l_u8UartBuffer[30] = { 0 };
int l_i32Status = -1;
l_i32RetSize = u16CMPLX_vFrameEncode((uint32_t)l_u32Id, (uint8_t*)&g_pu8UartBuffer[ecuUART_PKT_HEADER_u8], (int32_t)l_eRetCode, l_u8UartBuffer, 30);
l_i32Status = IVEC_ECUUartWrite(&__gprv_UartCcHandle, l_u8UartBuffer, l_i32RetSize);
}
xECU_WriteDataOverCAN(&g_xCanHandle, &g_pu8UartBuffer[ecuUART_PKT_HEADER_u8], l_u32Id, l_eRetCode, 0); xECU_WriteDataOverCAN(&g_xCanHandle, &g_pu8UartBuffer[ecuUART_PKT_HEADER_u8], l_u32Id, l_eRetCode, 0);
} }
@ -706,18 +714,7 @@ void vRTE_ProcessCanData(void)
l_xCanBuff.u32UlId = 0xabcdef; l_xCanBuff.u32UlId = 0xabcdef;
} }
l_i32RetSize = u16CMPLX_vFrameEncode((uint32_t)l_xCanBuff.u32UlId, (uint8_t*)&l_xCanBuff.u8Data[0], (int32_t)l_xCanBuff.u8Length, l_u8UartBuffer, 30); l_i32RetSize = u16CMPLX_vFrameEncode((uint32_t)l_xCanBuff.u32UlId, (uint8_t*)&l_xCanBuff.u8Data[0], (int32_t)l_xCanBuff.u8Length, l_u8UartBuffer, 30);
// if(l_xCanBuff.u32UlId == g_u32CanId)
// {
// l_u8UartBuffer[4] = 0Xab;
// l_u8UartBuffer[5] = 0Xcd;
// l_u8UartBuffer[6] = 0Xef;
// l_u8UartBuffer[7] = 0X00;
// }
l_i32Status = IVEC_ECUUartWrite(&__gprv_UartCcHandle, l_u8UartBuffer, l_i32RetSize); l_i32Status = IVEC_ECUUartWrite(&__gprv_UartCcHandle, l_u8UartBuffer, l_i32RetSize);
// if(l_i32Status != 0)
// {
// xECU_WriteDataOverCAN(&g_xCanHandle, NULL , 0x10, 1, 0);
// }
#endif #endif
iECU_UartInitiateTransmit(&g_xUartHandle, (uint32_t)l_xCanBuff.u32UlId, (uint8_t*)&l_xCanBuff.u8Data[0], (uint8_t)l_xCanBuff.u8Length); iECU_UartInitiateTransmit(&g_xUartHandle, (uint32_t)l_xCanBuff.u32UlId, (uint8_t*)&l_xCanBuff.u8Data[0], (uint8_t)l_xCanBuff.u8Length);