/*utils.c
 * @Created on: 22-Jan-2024
 * @Author: Vecmocon Technology
 */

#include <utils/utils.h>
#include "../Generated Codes/ti_msp_config.h"

static volatile uint32_t g_vrefInitFlag = 0;
volatile int g_i32TickCnt;
uint8_t g_systickInitFlag_u8 = 0;

static const DL_VREF_Config g_dlVrefConfig = {
    .vrefEnable     = DL_VREF_ENABLE_DISABLE,
    .bufConfig      = DL_VREF_BUFCONFIG_OUTPUT_2_5V,
    .shModeEnable   = DL_VREF_SHMODE_DISABLE,
    .holdCycleCount = DL_VREF_HOLD_MIN,
    .shCycleCount   = DL_VREF_SH_MIN,
};

static const DL_VREF_ClockConfig g_dlVrefClockConfig = {
    .clockSel      = DL_VREF_CLOCK_LFCLK,
    .divideRatio   = DL_VREF_CLOCK_DIVIDE_1,
};

/* Systick Initialization */
IVEC_CoreStatus_e xMCAL_SystickInit(IVEC_SystickPeriod_e eTick)
{
    SysTick_Config(eTick);
    NVIC_SetPriority(SysTick_IRQn, 0);

    g_systickInitFlag_u8 = 1;

    return IVEC_CORE_STATUS_SUCCESS;
}

static const DL_SYSCTL_SYSPLLConfig g_dlSysPllConfig = {
    .inputFreq     = DL_SYSCTL_SYSPLL_INPUT_FREQ_16_32_MHZ,
    .rDivClk2x     = 1,
    .rDivClk1      = 0,
    .rDivClk0      = 0,
    .enableCLK2x   = DL_SYSCTL_SYSPLL_CLK2X_DISABLE,
    .enableCLK1    = DL_SYSCTL_SYSPLL_CLK1_DISABLE,
    .enableCLK0    = DL_SYSCTL_SYSPLL_CLK0_ENABLE,
    .sysPLLMCLK    = DL_SYSCTL_SYSPLL_MCLK_CLK0,
    .sysPLLRef     = DL_SYSCTL_SYSPLL_REF_HFCLK,
    .qDiv          = 5,
    .pDiv          = DL_SYSCTL_SYSPLL_PDIV_1,
};

/* System Control Initialization */
IVEC_CoreStatus_e xMCAL_SysctlInit(uint8_t u8ClkSrc, uint8_t u8LowPowerMode)
{
    if ((u8LowPowerMode != IVEC_STANDBY0) && (u8LowPowerMode != IVEC_SLEEP0))
        return IVEC_CORE_STATUS_INIT_FAIL;

    if ((u8ClkSrc != IVEC_HFXT) && (u8ClkSrc != IVEC_SYSOSC))
        return IVEC_CORE_STATUS_INIT_FAIL;

    if (u8LowPowerMode == IVEC_STANDBY0)
    {
        DL_SYSCTL_setPowerPolicySTANDBY0();
        DL_SYSCTL_setBORThreshold(DL_SYSCTL_BOR_THRESHOLD_LEVEL_0);
        DL_SYSCTL_setFlashWaitState(DL_SYSCTL_FLASH_WAIT_STATE_2);
    }
    else if (u8LowPowerMode == IVEC_SLEEP0)
    {
        DL_SYSCTL_setBORThreshold(DL_SYSCTL_BOR_THRESHOLD_LEVEL_0);
        DL_SYSCTL_setFlashWaitState(DL_SYSCTL_FLASH_WAIT_STATE_2);
    }

    if (u8ClkSrc == IVEC_HFXT)
    {
        DL_SYSCTL_setBORThreshold(DL_SYSCTL_BOR_THRESHOLD_LEVEL_0);
        DL_SYSCTL_setFlashWaitState(DL_SYSCTL_FLASH_WAIT_STATE_2);
        DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
        DL_SYSCTL_disableHFXT();
        DL_SYSCTL_disableSYSPLL();
        DL_SYSCTL_setHFCLKSourceHFXTParams(DL_SYSCTL_HFXT_RANGE_16_32_MHZ, 10, true);
        DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *)&g_dlSysPllConfig);
        DL_SYSCTL_setULPCLKDivider(DL_SYSCTL_ULPCLK_DIV_2);
        DL_SYSCTL_setMCLKSource(SYSOSC, HSCLK, DL_SYSCTL_HSCLK_SOURCE_SYSPLL);
    }
    else if (u8ClkSrc == IVEC_SYSOSC)
    {
        DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
        DL_SYSCTL_disableHFXT();
        DL_SYSCTL_disableSYSPLL();
        DL_SYSCTL_setHFCLKSourceHFXTParams(DL_SYSCTL_HFXT_RANGE_16_32_MHZ, 50, true);
        DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *)&g_dlSysPllConfig);
        DL_SYSCTL_setHFCLKDividerForMFPCLK(DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_6);
        DL_SYSCTL_enableMFCLK();
        DL_SYSCTL_enableMFPCLK();
        DL_SYSCTL_setMFPCLKSource(DL_SYSCTL_MFPCLK_SOURCE_SYSOSC);
    }

    return IVEC_CORE_STATUS_SUCCESS;
}

void SysTick_Handler(void)
{
    g_i32TickCnt++;
}

int32_t i32MCAL_GetTicks()
{
    return g_i32TickCnt;
}

void vMCAL_DelayTicks(int32_t i32DelayMs)
{
    int32_t l_i32CurrTick = i32MCAL_GetTicks();

    while ((i32MCAL_GetTicks() - l_i32CurrTick) < i32DelayMs)
    {
        /* Wait */
    }
}

void vMCAL_McuInit(void)
{
    SYSCFG_DL_initPower();
    SYSCFG_DL_GPIO_init();
 }

void vMCAL_DelayUs(uint32_t u32Us)
{
    delay_cycles(32 * u32Us);
}

IVEC_McalStatus_e xMCAL_VrefInit(void)
{
    if (g_vrefInitFlag == 0)
    {
        DL_VREF_setClockConfig(VREF, (DL_VREF_ClockConfig *)&g_dlVrefClockConfig);
        DL_VREF_configReference(VREF, (DL_VREF_Config *)&g_dlVrefConfig);
        delay_cycles(320);
        g_vrefInitFlag = 1;
        return IVEC_MCAL_STATUS_SUCCESS;
    }
    else
    {
        return IVEC_MCAL_STATUS_INIT_FAIL;
    }
}

void vMCAL_SoftReset(void)
{
    DL_SYSCTL_resetDevice(DL_SYSCTL_RESET_CPU);
}