///* USER CODE BEGIN Header */
///**
//  ******************************************************************************
//  * @file    adc_dma.c
//  * @brief   This file provides code for the configuration
//  *          of the ADC instances.
//  * @data    1-feb-2024
//  * @Author  Vecmocon Technology
//  ******************************************************************************
//  */
///* USER CODE END Header */
//
///* Includes ------------------------------------------------------------------*/
//#include <Core\Include\ivec_mcal_adc_dma.h>
//
//static volatile bool b_AdcInitFlag = 0;   /*!< ADC initialization flag  */
//static volatile bool b_AdcStartFlag =0;   /*!< ADC start - stop flag  */
//static volatile bool b_DmaFlag =0;        /*!< DMA initialization flag */
//static volatile bool b_DmaStart =0;       /*!< DMA initialization flag */
//
///**
// * @brief  Configuration for ADC12_0 clock.
// */
//static const DL_ADC12_ClockConfig gADC12_1ClockConfig = {
//    .clockSel       = DL_ADC12_CLOCK_SYSOSC,
//    .divideRatio    = DL_ADC12_CLOCK_DIVIDE_1,
//    .freqRange      = DL_ADC12_CLOCK_FREQ_RANGE_24_TO_32,
//};
//
//
///**
// * @brief  Configuration for DMA.
// */
//static const DL_DMA_Config gDMA_CH0Config = {
//    .transferMode   = DL_DMA_SINGLE_TRANSFER_MODE,
//    .extendedMode   = DL_DMA_NORMAL_MODE,
//    .destIncrement  = DL_DMA_ADDR_UNCHANGED,
//    .srcIncrement   = DL_DMA_ADDR_UNCHANGED,
//    .destWidth      = DL_DMA_WIDTH_WORD,
//    .srcWidth       = DL_DMA_WIDTH_WORD,
//    .trigger        = ADC12_1_INST_DMA_TRIGGER,
//    .triggerType    = DL_DMA_TRIGGER_TYPE_EXTERNAL,
//};
//
//
//
///**
//  * @brief   Initlization ADC with DMA
//  * @note    Interruptions enabled in this function
//  * @param   adc_inst ADC handle
//  * @retval  IVEC MCAL status
//  */
//IVEC_McalStatus_e xMCAL_AdcInit(ADC12_Regs* const adc_inst)
//{
//    assert(adc_inst == ADC1);
//    if(b_AdcInitFlag == 0)
//    {
//        DL_ADC12_setClockConfig(ADC1, (DL_ADC12_ClockConfig *) &gADC12_1ClockConfig);
//        DL_ADC12_initSingleSample(ADC1, DL_ADC12_REPEAT_MODE_ENABLED, DL_ADC12_SAMPLING_SOURCE_AUTO, DL_ADC12_TRIG_SRC_SOFTWARE,DL_ADC12_SAMP_CONV_RES_12_BIT, DL_ADC12_SAMP_CONV_DATA_FORMAT_UNSIGNED);
//        DL_ADC12_configConversionMem(ADC1, DL_ADC12_MEM_IDX_0,
//        ADC12_MEMCTL_CHANSEL_CHAN_0, ADC12_MEMCTL_VRSEL_VDDA, ADC12_MEMCTL_STIME_SEL_SCOMP0, ADC12_MEMCTL_AVGEN_DISABLE,
//        ADC12_MEMCTL_BCSEN_DISABLE, ADC12_MEMCTL_TRIG_AUTO_NEXT, ADC12_MEMCTL_WINCOMP_DISABLE);
//        DL_ADC12_enableFIFO(ADC1);
//        DL_ADC12_setPowerDownMode(ADC1,ADC12_CTL0_PWRDN_MANUAL);
//        DL_ADC12_setSampleTime0(ADC1,dmaSAMPLETIME_u16);
//        DL_ADC12_enableDMA(ADC1);
//        DL_ADC12_setDMASamplesCnt(ADC1,dmaSAMPLECNT_u8);
//        DL_ADC12_enableDMATrigger(ADC1,(ADC12_DMA_TRIG_IMASK_MEMRESIFG7_SET));
//        DL_ADC12_clearInterruptStatus(ADC1,(ADC12_CPU_INT_IMASK_DMADONE_SET));
//        DL_ADC12_enableInterrupt(ADC1,(ADC12_CPU_INT_IMASK_DMADONE_SET));
//        DL_ADC12_enableConversions(ADC1);
//        b_AdcInitFlag =1;
//        return IVEC_MCAL_STATUS_SUCCESS;
//     }
//    else
//        return IVEC_MCAL_STATUS_INIT_FAIL;
//}
//
//
///**
//  * @brief  De-Initialize the ADC peripheral to their default reset values
//  * @param  adc_inst ADC handle
//  * @retval IVEC MCAL status
//  */
//IVEC_McalStatus_e xMCAL_AdcDeInit(ADC12_Regs* const adc_inst)
//{
//    assert(adc_inst == ADC1);
//    if(b_AdcInitFlag == 1 )
//    {
//       b_AdcInitFlag = 0;
//       return IVEC_MCAL_STATUS_SUCCESS;
//     }
//  else
//      return IVEC_MCAL_STATUS_INIT_FAIL;
//}
//
///**
//  * @brief  Enable ADC, start conversion of regular group.
//  * @note   Interruptions enabled in this function: None.
//  * @param  adc_inst ADC handle
//  * @retval IVEC MCAL status
//  */
//IVEC_McalStatus_e xMCAL_AdcStart(ADC12_Regs* const adc_inst)
//{
//    assert(adc_inst == ADC1);
//    if (b_AdcStartFlag == 0)
//    {
//        DL_ADC12_startConversion(adc_inst);
//        b_AdcStartFlag =1;
//        return IVEC_MCAL_STATUS_SUCCESS;
//    }
//    else
//        return IVEC_MCAL_STATUS_INIT_FAIL;
//}
//
///**
//  * @brief  Stop ADC conversion of regular group.
//  * @param  adc_inst ADC handle
//  * @retval IVEC MCAL status
//  */
//IVEC_McalStatus_e xMCAL_AdcStop(ADC12_Regs* const adc_inst)
//{
//    assert(adc_inst == ADC1);
//    if (b_AdcStartFlag == 1)
//    {
//        DL_ADC12_stopConversion(adc_inst);
//        b_AdcStartFlag = 0;
//        return IVEC_MCAL_STATUS_SUCCESS;
//    }
//    else
//        return IVEC_MCAL_STATUS_INIT_FAIL;
//}
//
//
///**
//  * @brief   Initlization of DMA for ADC
//  * @note    Interruptions enabled in this function
//  * @param   adc_inst ADC handle
//  * @retval  IVEC MCAL status
//  */
//IVEC_McalStatus_e xMCAL_DmaInit(void)
//{
//    if (b_DmaFlag==0)
//    {
//        DL_DMA_initChannel(DMA, dmaCHID_u8 , (DL_DMA_Config *) &gDMA_CH0Config);
//        DL_DMA_clearInterruptStatus(DMA, DMA_CPU_INT_IMASK_DMACH0_SET);
//        DL_DMA_enableInterrupt(DMA, DMA_CPU_INT_IMASK_DMACH0_SET);
//        DL_DMA_clearInterruptStatus(DMA, DMA_CPU_INT_IMASK_PREIRQCH0_SET);
//        DL_DMA_Full_Ch_setEarlyInterruptThreshold(DMA, dmaCHID_u8, DL_DMA_EARLY_INTERRUPT_THRESHOLD_HALF);
//        DL_DMA_enableInterrupt(DMA, DMA_CPU_INT_IMASK_PREIRQCH0_SET);
//        b_DmaFlag=1;
//        return IVEC_MCAL_STATUS_SUCCESS;
//    }
//    else
//        return IVEC_MCAL_STATUS_INIT_FAIL;
//
//}
//
///**
//  * @brief  De-Initialize the DMA to their default reset values
//  * @param  adc_inst ADC handle
//  * @retval IVEC MCAL status
//  */
//IVEC_McalStatus_e xMCAL_DmaDeInit(void)
//{
//    if(b_DmaFlag == 1 )
//    {
//        b_DmaFlag=0;
//        return IVEC_MCAL_STATUS_SUCCESS;
//    }
//    else
//        return IVEC_MCAL_STATUS_INIT_FAIL;
//}
//
///**
//  * @brief  Enable DMA, start transfer from ADC to DMA of regular group.
//  * @note   Interruptions enabled in this function: None.
//  * @param  u8Channel  use to pass the DMA channel
//  * @param  p_u16adcDma  use to get the ADC raw
//  * @retval IVEC MCAL status
//  */
//IVEC_McalStatus_e xMCAL_DmaStart(const uint8_t u8channel ,uint16_t* p_u16adcDma)
//{
//    assert(b_DmaStart == 0);
//    static uint32_t l_u32Data[2];
//    DL_DMA_setSrcAddr(DMA, dmaCHID_u8, (uint32_t)DL_ADC12_getFIFOAddress(ADC1));
//    DL_DMA_setDestAddr(DMA, dmaCHID_u8, (uint32_t)&l_u32Data[0]);
//    DL_DMA_setTransferSize(DMA, dmaCHID_u8, u8channel);
//    DL_DMA_enableChannel(DMA, dmaCHID_u8);
//    DL_ADC12_enableDMA(ADC1);
//    *p_u16adcDma = l_u32Data[0];
//    return IVEC_MCAL_STATUS_SUCCESS;
//}
//
///**
//  * @brief  Function use to set the DMA channel
//  * @param  u8Channel  use to pass the DMA channel
//  * @retval IVEC MCAL status
//  */
//IVEC_McalStatus_e xMCAL_DmaStop(void)
//{
//    if(b_DmaStart == 0)
//    {
//       b_DmaStart =1;
//       return IVEC_MCAL_STATUS_SUCCESS;
//    }
//    else
//        return IVEC_MCAL_STATUS_INIT_FAIL;
//}
//
///**
//  * @brief  ADC call back function
//  * @note  Interruptions enabled in this function
//  */
//void _prv_adccallback()
//{
//    switch (DL_ADC12_getPendingInterrupt(ADC1))
//    {
//        case DL_ADC12_IIDX_DMA_DONE:
//            break;
//        default:
//            break;
//    }
//}
///**
//  * @brief ADC IRQ handler
//  */
//void ADC1_IRQHandler()
//{
//    _prv_adccallback();
//}
//