233 lines
7.3 KiB
C
233 lines
7.3 KiB
C
///* USER CODE BEGIN Header */
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///**
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// ******************************************************************************
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// * @file adc_dma.c
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// * @brief This file provides code for the configuration
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// * of the ADC instances.
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// * @data 1-feb-2024
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// * @Author Vecmocon Technology
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// ******************************************************************************
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// */
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///* USER CODE END Header */
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//
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///* Includes ------------------------------------------------------------------*/
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//#include <Core\Include\ivec_mcal_adc_dma.h>
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//
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//static volatile bool b_AdcInitFlag = 0; /*!< ADC initialization flag */
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//static volatile bool b_AdcStartFlag =0; /*!< ADC start - stop flag */
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//static volatile bool b_DmaFlag =0; /*!< DMA initialization flag */
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//static volatile bool b_DmaStart =0; /*!< DMA initialization flag */
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//
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///**
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// * @brief Configuration for ADC12_0 clock.
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// */
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//static const DL_ADC12_ClockConfig gADC12_1ClockConfig = {
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// .clockSel = DL_ADC12_CLOCK_SYSOSC,
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// .divideRatio = DL_ADC12_CLOCK_DIVIDE_1,
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// .freqRange = DL_ADC12_CLOCK_FREQ_RANGE_24_TO_32,
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//};
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//
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//
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///**
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// * @brief Configuration for DMA.
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// */
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//static const DL_DMA_Config gDMA_CH0Config = {
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// .transferMode = DL_DMA_SINGLE_TRANSFER_MODE,
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// .extendedMode = DL_DMA_NORMAL_MODE,
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// .destIncrement = DL_DMA_ADDR_UNCHANGED,
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// .srcIncrement = DL_DMA_ADDR_UNCHANGED,
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// .destWidth = DL_DMA_WIDTH_WORD,
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// .srcWidth = DL_DMA_WIDTH_WORD,
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// .trigger = ADC12_1_INST_DMA_TRIGGER,
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// .triggerType = DL_DMA_TRIGGER_TYPE_EXTERNAL,
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//};
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//
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//
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//
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///**
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// * @brief Initlization ADC with DMA
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// * @note Interruptions enabled in this function
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// * @param adc_inst ADC handle
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// * @retval IVEC MCAL status
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// */
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//IVEC_McalStatus_e xMCAL_AdcInit(ADC12_Regs* const adc_inst)
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//{
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// assert(adc_inst == ADC1);
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// if(b_AdcInitFlag == 0)
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// {
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// DL_ADC12_setClockConfig(ADC1, (DL_ADC12_ClockConfig *) &gADC12_1ClockConfig);
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// DL_ADC12_initSingleSample(ADC1, DL_ADC12_REPEAT_MODE_ENABLED, DL_ADC12_SAMPLING_SOURCE_AUTO, DL_ADC12_TRIG_SRC_SOFTWARE,DL_ADC12_SAMP_CONV_RES_12_BIT, DL_ADC12_SAMP_CONV_DATA_FORMAT_UNSIGNED);
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// DL_ADC12_configConversionMem(ADC1, DL_ADC12_MEM_IDX_0,
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// ADC12_MEMCTL_CHANSEL_CHAN_0, ADC12_MEMCTL_VRSEL_VDDA, ADC12_MEMCTL_STIME_SEL_SCOMP0, ADC12_MEMCTL_AVGEN_DISABLE,
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// ADC12_MEMCTL_BCSEN_DISABLE, ADC12_MEMCTL_TRIG_AUTO_NEXT, ADC12_MEMCTL_WINCOMP_DISABLE);
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// DL_ADC12_enableFIFO(ADC1);
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// DL_ADC12_setPowerDownMode(ADC1,ADC12_CTL0_PWRDN_MANUAL);
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// DL_ADC12_setSampleTime0(ADC1,dmaSAMPLETIME_u16);
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// DL_ADC12_enableDMA(ADC1);
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// DL_ADC12_setDMASamplesCnt(ADC1,dmaSAMPLECNT_u8);
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// DL_ADC12_enableDMATrigger(ADC1,(ADC12_DMA_TRIG_IMASK_MEMRESIFG7_SET));
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// DL_ADC12_clearInterruptStatus(ADC1,(ADC12_CPU_INT_IMASK_DMADONE_SET));
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// DL_ADC12_enableInterrupt(ADC1,(ADC12_CPU_INT_IMASK_DMADONE_SET));
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// DL_ADC12_enableConversions(ADC1);
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// b_AdcInitFlag =1;
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// return IVEC_MCAL_STATUS_SUCCESS;
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// }
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// else
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// return IVEC_MCAL_STATUS_INIT_FAIL;
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//}
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//
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//
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///**
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// * @brief De-Initialize the ADC peripheral to their default reset values
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// * @param adc_inst ADC handle
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// * @retval IVEC MCAL status
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// */
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//IVEC_McalStatus_e xMCAL_AdcDeInit(ADC12_Regs* const adc_inst)
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//{
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// assert(adc_inst == ADC1);
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// if(b_AdcInitFlag == 1 )
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// {
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// b_AdcInitFlag = 0;
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// return IVEC_MCAL_STATUS_SUCCESS;
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// }
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// else
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// return IVEC_MCAL_STATUS_INIT_FAIL;
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//}
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//
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///**
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// * @brief Enable ADC, start conversion of regular group.
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// * @note Interruptions enabled in this function: None.
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// * @param adc_inst ADC handle
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// * @retval IVEC MCAL status
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// */
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//IVEC_McalStatus_e xMCAL_AdcStart(ADC12_Regs* const adc_inst)
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//{
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// assert(adc_inst == ADC1);
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// if (b_AdcStartFlag == 0)
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// {
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// DL_ADC12_startConversion(adc_inst);
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// b_AdcStartFlag =1;
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// return IVEC_MCAL_STATUS_SUCCESS;
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// }
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// else
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// return IVEC_MCAL_STATUS_INIT_FAIL;
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//}
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//
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///**
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// * @brief Stop ADC conversion of regular group.
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// * @param adc_inst ADC handle
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// * @retval IVEC MCAL status
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// */
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//IVEC_McalStatus_e xMCAL_AdcStop(ADC12_Regs* const adc_inst)
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//{
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// assert(adc_inst == ADC1);
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// if (b_AdcStartFlag == 1)
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// {
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// DL_ADC12_stopConversion(adc_inst);
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// b_AdcStartFlag = 0;
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// return IVEC_MCAL_STATUS_SUCCESS;
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// }
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// else
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// return IVEC_MCAL_STATUS_INIT_FAIL;
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//}
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//
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//
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///**
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// * @brief Initlization of DMA for ADC
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// * @note Interruptions enabled in this function
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// * @param adc_inst ADC handle
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// * @retval IVEC MCAL status
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// */
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//IVEC_McalStatus_e xMCAL_DmaInit(void)
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//{
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// if (b_DmaFlag==0)
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// {
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// DL_DMA_initChannel(DMA, dmaCHID_u8 , (DL_DMA_Config *) &gDMA_CH0Config);
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// DL_DMA_clearInterruptStatus(DMA, DMA_CPU_INT_IMASK_DMACH0_SET);
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// DL_DMA_enableInterrupt(DMA, DMA_CPU_INT_IMASK_DMACH0_SET);
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// DL_DMA_clearInterruptStatus(DMA, DMA_CPU_INT_IMASK_PREIRQCH0_SET);
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// DL_DMA_Full_Ch_setEarlyInterruptThreshold(DMA, dmaCHID_u8, DL_DMA_EARLY_INTERRUPT_THRESHOLD_HALF);
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// DL_DMA_enableInterrupt(DMA, DMA_CPU_INT_IMASK_PREIRQCH0_SET);
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// b_DmaFlag=1;
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// return IVEC_MCAL_STATUS_SUCCESS;
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// }
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// else
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// return IVEC_MCAL_STATUS_INIT_FAIL;
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//
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//}
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//
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///**
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// * @brief De-Initialize the DMA to their default reset values
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// * @param adc_inst ADC handle
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// * @retval IVEC MCAL status
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// */
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//IVEC_McalStatus_e xMCAL_DmaDeInit(void)
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//{
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// if(b_DmaFlag == 1 )
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// {
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// b_DmaFlag=0;
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// return IVEC_MCAL_STATUS_SUCCESS;
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// }
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// else
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// return IVEC_MCAL_STATUS_INIT_FAIL;
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//}
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//
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///**
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// * @brief Enable DMA, start transfer from ADC to DMA of regular group.
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// * @note Interruptions enabled in this function: None.
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// * @param u8Channel use to pass the DMA channel
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// * @param p_u16adcDma use to get the ADC raw
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// * @retval IVEC MCAL status
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// */
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//IVEC_McalStatus_e xMCAL_DmaStart(const uint8_t u8channel ,uint16_t* p_u16adcDma)
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//{
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// assert(b_DmaStart == 0);
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// static uint32_t l_u32Data[2];
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// DL_DMA_setSrcAddr(DMA, dmaCHID_u8, (uint32_t)DL_ADC12_getFIFOAddress(ADC1));
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// DL_DMA_setDestAddr(DMA, dmaCHID_u8, (uint32_t)&l_u32Data[0]);
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// DL_DMA_setTransferSize(DMA, dmaCHID_u8, u8channel);
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// DL_DMA_enableChannel(DMA, dmaCHID_u8);
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// DL_ADC12_enableDMA(ADC1);
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// *p_u16adcDma = l_u32Data[0];
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// return IVEC_MCAL_STATUS_SUCCESS;
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//}
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//
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///**
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// * @brief Function use to set the DMA channel
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// * @param u8Channel use to pass the DMA channel
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// * @retval IVEC MCAL status
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// */
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//IVEC_McalStatus_e xMCAL_DmaStop(void)
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//{
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// if(b_DmaStart == 0)
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// {
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// b_DmaStart =1;
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// return IVEC_MCAL_STATUS_SUCCESS;
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// }
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// else
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// return IVEC_MCAL_STATUS_INIT_FAIL;
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//}
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//
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///**
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// * @brief ADC call back function
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// * @note Interruptions enabled in this function
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// */
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//void _prv_adccallback()
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//{
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// switch (DL_ADC12_getPendingInterrupt(ADC1))
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// {
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// case DL_ADC12_IIDX_DMA_DONE:
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// break;
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// default:
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// break;
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// }
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//}
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///**
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// * @brief ADC IRQ handler
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// */
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//void ADC1_IRQHandler()
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//{
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// _prv_adccallback();
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//}
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//
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