547 lines
18 KiB
C
547 lines
18 KiB
C
/*
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* Copyright (c) 2023, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* ============ ti_msp_dl_config.c =============
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* Configured MSPM0 DriverLib module definitions
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*
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* DO NOT EDIT - This file is generated for the MSPM0G350X
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* by the SysConfig tool.
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*/
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///* Port definition for Pin Group GPIO_tick */
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//#define GPIO_tick_PORT (GPIOA)
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//
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///* Defines for PIN_0: GPIOA.2 with pinCMx 7 on package pin 8 */
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//#define tick_PIN_0_PIN (0x00004000)
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#include "ti_msp_dl_config.h"
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#include "../../utils/utils.h"
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DL_TimerA_backupConfig gCAPTURE_0Backup;
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DL_TimerA_backupConfig gTIMER_1Backup;
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DL_MCAN_backupConfig gMCAN0Backup;
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/*
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* ======== SYSCFG_DL_init ========
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* Perform any initialization needed before using any board APIs
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*/
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SYSCONFIG_WEAK void SYSCFG_DL_init(void)
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{
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SYSCFG_DL_initPower();
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SYSCFG_DL_GPIO_init();
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/* Module-Specific Initializations*/
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SYSCFG_DL_SYSCTL_init();
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SYSCFG_DL_CAPTURE_0_init();
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SYSCFG_DL_TIMER_0_init();
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SYSCFG_DL_TIMER_1_init();
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SYSCFG_DL_UART_0_init();
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SYSCFG_DL_MCAN0_init();
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SYSCFG_DL_SYSCTL_CLK_init();
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/* Ensure backup structures have no valid state */
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gCAPTURE_0Backup.backupRdy = false;
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gTIMER_1Backup.backupRdy = false;
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gMCAN0Backup.backupRdy = false;
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}
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/*
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* User should take care to save and restore register configuration in application.
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* See Retention Configuration section for more details.
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*/
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SYSCONFIG_WEAK bool SYSCFG_DL_saveConfiguration(void)
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{
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bool retStatus = true;
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retStatus &= DL_TimerA_saveConfiguration(CAPTURE_0_INST, &gCAPTURE_0Backup);
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retStatus &= DL_TimerA_saveConfiguration(TIMER_1_INST, &gTIMER_1Backup);
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retStatus &= DL_MCAN_saveConfiguration(MCAN0_INST, &gMCAN0Backup);
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return retStatus;
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}
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SYSCONFIG_WEAK bool SYSCFG_DL_restoreConfiguration(void)
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{
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bool retStatus = true;
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retStatus &= DL_TimerA_restoreConfiguration(CAPTURE_0_INST, &gCAPTURE_0Backup, false);
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retStatus &= DL_TimerA_restoreConfiguration(TIMER_1_INST, &gTIMER_1Backup, false);
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retStatus &= DL_MCAN_restoreConfiguration(MCAN0_INST, &gMCAN0Backup);
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return retStatus;
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}
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SYSCONFIG_WEAK void SYSCFG_DL_initPower(void)
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{
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DL_GPIO_reset(GPIOA);
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DL_GPIO_reset(GPIOB);
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DL_TimerA_reset(CAPTURE_0_INST);
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DL_TimerG_reset(TIMER_0_INST);
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DL_TimerA_reset(TIMER_1_INST);
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DL_MCAN_reset(MCAN0_INST);
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#if UART_PIN_SELECTION == 1
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DL_UART_Main_reset(UART2);
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DL_UART_Main_enablePower(UART2);
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#elif UART_PIN_SELECTION == 2
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DL_UART_Main_reset(UART1);
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DL_UART_Main_enablePower(UART1);
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#elif UART_PIN_SELECTION == 3
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// UART1 pins
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DL_UART_Main_reset(UART1);
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DL_UART_Main_enablePower(UART1);
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DL_UART_Main_reset(UART2);
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DL_UART_Main_enablePower(UART2);
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DL_GPIO_initDigitalOutput(IOMUX_PINCM48);
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DL_GPIO_initDigitalOutput(IOMUX_PINCM45);
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DL_GPIO_initDigitalOutput(IOMUX_PINCM44);
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DL_GPIO_initDigitalOutput(IOMUX_PINCM43);
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DL_GPIO_initDigitalOutput(IOMUX_PINCM33);
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DL_GPIO_initDigitalOutput(IOMUX_PINCM32);
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DL_GPIO_initDigitalOutput(IOMUX_PINCM31);
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DL_GPIO_initDigitalOutput(IOMUX_PINCM26);
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DL_GPIO_initDigitalOutput(IOMUX_PINCM25);
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DL_GPIO_clearPins(GPIOB, GPIO_relay_pin_relay_1_PIN |
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GPIO_relay_pin_relay_2_PIN |
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GPIO_relay_pin_relay_3_PIN |
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GPIO_relay_pin_relay_4_PIN |
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GPIO_relay_pin_relay_5_PIN |
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GPIO_relay_pin_relay_6_PIN |
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GPIO_relay_pin_relay_7_PIN |
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GPIO_relay_pin_relay_8_PIN |
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GPIO_relay_pin_relay_9_PIN);
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DL_GPIO_enableOutput(GPIOB, GPIO_relay_pin_relay_1_PIN |
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GPIO_relay_pin_relay_2_PIN |
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GPIO_relay_pin_relay_3_PIN |
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GPIO_relay_pin_relay_4_PIN |
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GPIO_relay_pin_relay_5_PIN |
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GPIO_relay_pin_relay_6_PIN |
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GPIO_relay_pin_relay_7_PIN |
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GPIO_relay_pin_relay_8_PIN |
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GPIO_relay_pin_relay_9_PIN);
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#endif
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DL_GPIO_enablePower(GPIOA);
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DL_GPIO_enablePower(GPIOB);
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DL_TimerA_enablePower(CAPTURE_0_INST);
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DL_TimerG_enablePower(TIMER_0_INST);
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DL_TimerA_enablePower(TIMER_1_INST);
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DL_MCAN_enablePower(MCAN0_INST);
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delay_cycles(POWER_STARTUP_DELAY);
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}
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SYSCONFIG_WEAK void SYSCFG_DL_GPIO_init(void)
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{
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DL_GPIO_initPeripheralAnalogFunction(GPIO_HFXIN_IOMUX);
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DL_GPIO_initPeripheralAnalogFunction(GPIO_HFXOUT_IOMUX);
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DL_GPIO_initPeripheralInputFunction(GPIO_CAPTURE_0_C0_IOMUX,GPIO_CAPTURE_0_C0_IOMUX_FUNC);
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DL_GPIO_initPeripheralOutputFunction(
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GPIO_UART_0_IOMUX_TX, GPIO_UART_0_IOMUX_TX_FUNC);
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DL_GPIO_initPeripheralInputFunction(
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GPIO_UART_0_IOMUX_RX, GPIO_UART_0_IOMUX_RX_FUNC);
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DL_GPIO_initDigitalInputFeatures(GPIO_GRP_0_PIN_0_IOMUX,
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DL_GPIO_INVERSION_DISABLE, DL_GPIO_RESISTOR_NONE,
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DL_GPIO_HYSTERESIS_DISABLE, DL_GPIO_WAKEUP_DISABLE);
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// DL_GPIO_initDigitalOutput(GPIO_GRP_0_PIN_0_IOMUX);
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DL_GPIO_initPeripheralOutputFunction(
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GPIO_MCAN0_IOMUX_CAN_TX, GPIO_MCAN0_IOMUX_CAN_TX_FUNC);
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DL_GPIO_initPeripheralInputFunction(
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GPIO_MCAN0_IOMUX_CAN_RX, GPIO_MCAN0_IOMUX_CAN_RX_FUNC);
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// DL_GPIO_initDigitalOutput(IOMUX_PINCM31);
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//
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// DL_GPIO_clearPins(GPIOB, tick_PIN_0_PIN);
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// DL_GPIO_enableOutput(GPIOB, tick_PIN_0_PIN);
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}
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static const DL_SYSCTL_SYSPLLConfig gSYSPLLConfig = {
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.inputFreq = DL_SYSCTL_SYSPLL_INPUT_FREQ_16_32_MHZ,
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.rDivClk2x = 1,
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.rDivClk1 = 0,
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.rDivClk0 = 0,
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.enableCLK2x = DL_SYSCTL_SYSPLL_CLK2X_DISABLE,
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.enableCLK1 = DL_SYSCTL_SYSPLL_CLK1_DISABLE,
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.enableCLK0 = DL_SYSCTL_SYSPLL_CLK0_ENABLE,
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.sysPLLMCLK = DL_SYSCTL_SYSPLL_MCLK_CLK0,
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.sysPLLRef = DL_SYSCTL_SYSPLL_REF_HFCLK,
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.qDiv = 1,
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.pDiv = DL_SYSCTL_SYSPLL_PDIV_1
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};
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SYSCONFIG_WEAK void SYSCFG_DL_SYSCTL_init(void)
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{
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//Low Power Mode is configured to be SLEEP0
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DL_SYSCTL_setBORThreshold(DL_SYSCTL_BOR_THRESHOLD_LEVEL_0);
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DL_SYSCTL_setFlashWaitState(DL_SYSCTL_FLASH_WAIT_STATE_2);
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DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
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/* Set default configuration */
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DL_SYSCTL_disableHFXT();
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DL_SYSCTL_disableSYSPLL();
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DL_SYSCTL_setHFCLKSourceHFXTParams(DL_SYSCTL_HFXT_RANGE_16_32_MHZ,10, true);
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DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *) &gSYSPLLConfig);
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DL_SYSCTL_setULPCLKDivider(DL_SYSCTL_ULPCLK_DIV_1);
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DL_SYSCTL_setMCLKSource(SYSOSC, HSCLK, DL_SYSCTL_HSCLK_SOURCE_SYSPLL);
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}
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SYSCONFIG_WEAK void SYSCFG_DL_SYSCTL_CLK_init(void) {
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while ((DL_SYSCTL_getClockStatus() & (DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD
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| DL_SYSCTL_CLK_STATUS_HFCLK_GOOD
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| DL_SYSCTL_CLK_STATUS_HSCLK_GOOD
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| DL_SYSCTL_CLK_STATUS_LFOSC_GOOD))
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!= (DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD
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| DL_SYSCTL_CLK_STATUS_HFCLK_GOOD
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| DL_SYSCTL_CLK_STATUS_HSCLK_GOOD
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| DL_SYSCTL_CLK_STATUS_LFOSC_GOOD))
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{
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/* Ensure that clocks are in default POR configuration before initialization.
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* Additionally once LFXT is enabled, the internal LFOSC is disabled, and cannot
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* be re-enabled other than by executing a BOOTRST. */
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;
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}
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}
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/*
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* Timer clock configuration to be sourced by BUSCLK / (24000000 Hz)
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* timerClkFreq = (timerClkSrc / (timerClkDivRatio * (timerClkPrescale + 1)))
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* 12000000 Hz = 24000000 Hz / (1 * (1 + 1))
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*/
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static const DL_TimerA_ClockConfig gCAPTURE_0ClockConfig = {
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.clockSel = DL_TIMER_CLOCK_BUSCLK,
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.divideRatio = DL_TIMER_CLOCK_DIVIDE_1,
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.prescale = 1U
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};
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/*
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* Timer load value (where the counter starts from) is calculated as (timerPeriod * timerClockFreq) - 1
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* CAPTURE_0_INST_LOAD_VALUE = (0 ms * 12000000 Hz) - 1
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*/
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static const DL_TimerA_CaptureConfig gCAPTURE_0CaptureConfig = {
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.captureMode = DL_TIMER_CAPTURE_MODE_EDGE_TIME,
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.period = CAPTURE_0_INST_LOAD_VALUE,
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.startTimer = DL_TIMER_STOP,
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.edgeCaptMode = DL_TIMER_CAPTURE_EDGE_DETECTION_MODE_RISING,
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.inputChan = DL_TIMER_INPUT_CHAN_0,
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.inputInvMode = DL_TIMER_CC_INPUT_INV_NOINVERT,
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};
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SYSCONFIG_WEAK void SYSCFG_DL_CAPTURE_0_init(void) {
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DL_TimerA_setClockConfig(CAPTURE_0_INST,
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(DL_TimerA_ClockConfig *) &gCAPTURE_0ClockConfig);
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DL_TimerA_initCaptureMode(CAPTURE_0_INST,
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(DL_TimerA_CaptureConfig *) &gCAPTURE_0CaptureConfig);
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DL_TimerA_enableClock(CAPTURE_0_INST);
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}
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/*
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* Timer clock configuration to be sourced by LFCLK / (32768 Hz)
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* timerClkFreq = (timerClkSrc / (timerClkDivRatio * (timerClkPrescale + 1)))
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* 992.969696969697 Hz = 32768 Hz / (1 * (32 + 1))
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*/
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static const DL_TimerG_ClockConfig gTIMER_0ClockConfig = {
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.clockSel = DL_TIMER_CLOCK_LFCLK,
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.divideRatio = DL_TIMER_CLOCK_DIVIDE_1,
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.prescale = 32U,
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};
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/*
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* Timer load value (where the counter starts from) is calculated as (timerPeriod * timerClockFreq) - 1
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* TIMER_0_INST_LOAD_VALUE = (500 ms * 992.969696969697 Hz) - 1
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*/
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static const DL_TimerG_TimerConfig gTIMER_0TimerConfig = {
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.period = TIMER_0_INST_LOAD_VALUE,
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.timerMode = DL_TIMER_TIMER_MODE_PERIODIC,
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.startTimer = DL_TIMER_STOP,
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};
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SYSCONFIG_WEAK void SYSCFG_DL_TIMER_0_init(void) {
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DL_TimerG_setClockConfig(TIMER_0_INST,
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(DL_TimerG_ClockConfig *) &gTIMER_0ClockConfig);
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DL_TimerG_initTimerMode(TIMER_0_INST,
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(DL_TimerG_TimerConfig *) &gTIMER_0TimerConfig);
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DL_TimerG_enableInterrupt(TIMER_0_INST , DL_TIMERG_INTERRUPT_ZERO_EVENT);
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DL_TimerG_enableClock(TIMER_0_INST);
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}
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/*
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* Timer clock configuration to be sourced by LFCLK / (10922.666666666666 Hz)
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* timerClkFreq = (timerClkSrc / (timerClkDivRatio * (timerClkPrescale + 1)))
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* 10922.666666666666 Hz = 10922.666666666666 Hz / (3 * (0 + 1))
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*/
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static const DL_TimerA_ClockConfig gTIMER_1ClockConfig = {
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.clockSel = DL_TIMER_CLOCK_LFCLK,
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.divideRatio = DL_TIMER_CLOCK_DIVIDE_3,
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.prescale = 0U,
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};
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/*
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* Timer load value (where the counter starts from) is calculated as (timerPeriod * timerClockFreq) - 1
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* TIMER_1_INST_LOAD_VALUE = (100 ms * 10922.666666666666 Hz) - 1
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*/
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static const DL_TimerA_TimerConfig gTIMER_1TimerConfig = {
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.period = TIMER_1_INST_LOAD_VALUE,
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.timerMode = DL_TIMER_TIMER_MODE_PERIODIC,
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.startTimer = DL_TIMER_STOP,
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};
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SYSCONFIG_WEAK void SYSCFG_DL_TIMER_1_init(void) {
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DL_TimerA_setClockConfig(TIMER_1_INST,
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(DL_TimerA_ClockConfig *) &gTIMER_1ClockConfig);
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DL_TimerA_initTimerMode(TIMER_1_INST,
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(DL_TimerA_TimerConfig *) &gTIMER_1TimerConfig);
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DL_TimerA_enableInterrupt(TIMER_1_INST , DL_TIMERA_INTERRUPT_ZERO_EVENT);
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NVIC_SetPriority(TIMER_1_INST_INT_IRQN, 1);
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DL_TimerA_enableClock(TIMER_1_INST);
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}
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static const DL_UART_Main_ClockConfig gUART_0ClockConfig = {
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.clockSel = DL_UART_MAIN_CLOCK_BUSCLK,
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.divideRatio = DL_UART_MAIN_CLOCK_DIVIDE_RATIO_1
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};
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static const DL_UART_Main_Config gUART_0Config = {
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.mode = DL_UART_MAIN_MODE_NORMAL,
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.direction = DL_UART_MAIN_DIRECTION_TX_RX,
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.flowControl = DL_UART_MAIN_FLOW_CONTROL_NONE,
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.parity = DL_UART_MAIN_PARITY_NONE,
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.wordLength = DL_UART_MAIN_WORD_LENGTH_8_BITS,
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.stopBits = DL_UART_MAIN_STOP_BITS_ONE
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};
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SYSCONFIG_WEAK void SYSCFG_DL_UART_0_init(void)
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{
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DL_UART_Main_setClockConfig(UART_0_INST, (DL_UART_Main_ClockConfig *) &gUART_0ClockConfig);
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DL_UART_Main_init(UART_0_INST, (DL_UART_Main_Config *) &gUART_0Config);
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/*
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* Configure baud rate by setting oversampling and baud rate divisors.
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* Target baud rate: 115200
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* Actual baud rate: 115246.1
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*/
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DL_UART_Main_setOversampling(UART_0_INST, DL_UART_OVERSAMPLING_RATE_16X);
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DL_UART_Main_setBaudRateDivisor(UART_0_INST, UART_0_IBRD_24_MHZ_115200_BAUD, UART_0_FBRD_24_MHZ_115200_BAUD);
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DL_UART_Main_enable(UART_0_INST);
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}
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static const DL_MCAN_ClockConfig gMCAN0ClockConf = {
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.clockSel = DL_MCAN_FCLK_HFCLK,
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.divider = DL_MCAN_FCLK_DIV_1,
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};
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static const DL_MCAN_InitParams gMCAN0InitParams= {
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/* Initialize MCAN Init parameters. */
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.fdMode = false,
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.brsEnable = false,
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.txpEnable = false,
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.efbi = false,
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.pxhddisable = false,
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.darEnable = false,
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.wkupReqEnable = false,
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.autoWkupEnable = false,
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.emulationEnable = false,
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.tdcEnable = false,
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.wdcPreload = 255,
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/* Transmitter Delay Compensation parameters. */
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.tdcConfig.tdcf = 10,
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.tdcConfig.tdco = 6,
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};
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static const DL_MCAN_MsgRAMConfigParams gMCAN0MsgRAMConfigParams ={
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/* Standard ID Filter List Start Address. */
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.flssa = MCAN0_INST_MCAN_STD_ID_FILT_START_ADDR,
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/* List Size: Standard ID. */
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.lss = MCAN0_INST_MCAN_STD_ID_FILTER_NUM,
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/* Extended ID Filter List Start Address. */
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.flesa = MCAN0_INST_MCAN_EXT_ID_FILT_START_ADDR,
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/* List Size: Extended ID. */
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.lse = MCAN0_INST_MCAN_EXT_ID_FILTER_NUM,
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/* Tx Buffers Start Address. */
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.txStartAddr = MCAN0_INST_MCAN_TX_BUFF_START_ADDR,
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/* Number of Dedicated Transmit Buffers. */
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.txBufNum = MCAN0_INST_MCAN_TX_BUFF_SIZE,
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.txFIFOSize = 0,
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/* Tx Buffer Element Size. */
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.txBufMode = 0,
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.txBufElemSize = DL_MCAN_ELEM_SIZE_64BYTES,
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/* Tx Event FIFO Start Address. */
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.txEventFIFOStartAddr = MCAN0_INST_MCAN_TX_EVENT_START_ADDR,
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/* Event FIFO Size. */
|
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.txEventFIFOSize = MCAN0_INST_MCAN_TX_EVENT_SIZE,
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/* Level for Tx Event FIFO watermark interrupt. */
|
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.txEventFIFOWaterMark = 3,
|
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/* Rx FIFO0 Start Address. */
|
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.rxFIFO0startAddr = MCAN0_INST_MCAN_FIFO_0_START_ADDR,
|
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/* Number of Rx FIFO elements. */
|
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.rxFIFO0size = MCAN0_INST_MCAN_FIFO_0_NUM,
|
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/* Rx FIFO0 Watermark. */
|
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.rxFIFO0waterMark = 3,
|
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.rxFIFO0OpMode = 0,
|
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/* Rx FIFO1 Start Address. */
|
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.rxFIFO1startAddr = MCAN0_INST_MCAN_FIFO_1_START_ADDR,
|
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/* Number of Rx FIFO elements. */
|
|
.rxFIFO1size = MCAN0_INST_MCAN_FIFO_1_NUM,
|
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/* Level for Rx FIFO 1 watermark interrupt. */
|
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.rxFIFO1waterMark = 3,
|
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/* FIFO blocking mode. */
|
|
.rxFIFO1OpMode = 0,
|
|
/* Rx Buffer Start Address. */
|
|
.rxBufStartAddr = MCAN0_INST_MCAN_RX_BUFF_START_ADDR,
|
|
/* Rx Buffer Element Size. */
|
|
.rxBufElemSize = DL_MCAN_ELEM_SIZE_64BYTES,
|
|
/* Rx FIFO0 Element Size. */
|
|
.rxFIFO0ElemSize = DL_MCAN_ELEM_SIZE_64BYTES,
|
|
/* Rx FIFO1 Element Size. */
|
|
.rxFIFO1ElemSize = DL_MCAN_ELEM_SIZE_64BYTES,
|
|
};
|
|
|
|
|
|
|
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static const DL_MCAN_BitTimingParams gMCAN0BitTimes = {
|
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/* Arbitration Baud Rate Pre-scaler. */
|
|
.nomRatePrescalar = 0,
|
|
/* Arbitration Time segment before sample point. */
|
|
.nomTimeSeg1 = 40,
|
|
/* Arbitration Time segment after sample point. */
|
|
.nomTimeSeg2 = 5,
|
|
/* Arbitration (Re)Synchronization Jump Width Range. */
|
|
.nomSynchJumpWidth = 5,
|
|
/* Data Baud Rate Pre-scaler. */
|
|
.dataRatePrescalar = 0,
|
|
/* Data Time segment before sample point. */
|
|
.dataTimeSeg1 = 0,
|
|
/* Data Time segment after sample point. */
|
|
.dataTimeSeg2 = 0,
|
|
/* Data (Re)Synchronization Jump Width. */
|
|
.dataSynchJumpWidth = 0,
|
|
};
|
|
|
|
|
|
SYSCONFIG_WEAK void SYSCFG_DL_MCAN0_init(void) {
|
|
DL_MCAN_RevisionId revid_MCAN0;
|
|
|
|
DL_MCAN_enableModuleClock(MCAN0_INST);
|
|
|
|
DL_MCAN_setClockConfig(MCAN0_INST, (DL_MCAN_ClockConfig *) &gMCAN0ClockConf);
|
|
|
|
/* Get MCANSS Revision ID. */
|
|
DL_MCAN_getRevisionId(MCAN0_INST, &revid_MCAN0);
|
|
|
|
/* Wait for Memory initialization to be completed. */
|
|
while(false == DL_MCAN_isMemInitDone(MCAN0_INST));
|
|
|
|
/* Put MCAN in SW initialization mode. */
|
|
|
|
DL_MCAN_setOpMode(MCAN0_INST, DL_MCAN_OPERATION_MODE_SW_INIT);
|
|
|
|
/* Wait till MCAN is not initialized. */
|
|
while (DL_MCAN_OPERATION_MODE_SW_INIT != DL_MCAN_getOpMode(MCAN0_INST));
|
|
|
|
/* Initialize MCAN module. */
|
|
DL_MCAN_init(MCAN0_INST, (DL_MCAN_InitParams *) &gMCAN0InitParams);
|
|
|
|
|
|
/* Configure Bit timings. */
|
|
DL_MCAN_setBitTime(MCAN0_INST, (DL_MCAN_BitTimingParams*) &gMCAN0BitTimes);
|
|
|
|
/* Configure Message RAM Sections */
|
|
DL_MCAN_msgRAMConfig(MCAN0_INST, (DL_MCAN_MsgRAMConfigParams*) &gMCAN0MsgRAMConfigParams);
|
|
|
|
|
|
|
|
/* Set Extended ID Mask. */
|
|
DL_MCAN_setExtIDAndMask(MCAN0_INST, MCAN0_INST_MCAN_EXT_ID_AND_MASK );
|
|
|
|
/* Loopback mode */
|
|
|
|
/* Take MCAN out of the SW initialization mode */
|
|
DL_MCAN_setOpMode(MCAN0_INST, DL_MCAN_OPERATION_MODE_NORMAL);
|
|
|
|
while (DL_MCAN_OPERATION_MODE_NORMAL != DL_MCAN_getOpMode(MCAN0_INST));
|
|
|
|
|
|
}
|
|
|