134 lines
3.7 KiB
C
134 lines
3.7 KiB
C
#include "ivec_mcal_wdt.h"
|
|
|
|
static volatile bool b_WDInitFlag;
|
|
|
|
|
|
IVEC_McalStatus_e xMCAL_WatchdogInit(MCAL_WWDT_TIMER timer)
|
|
{
|
|
DL_WWDT_CLOCK_DIVIDE Clk_Div;
|
|
DL_WWDT_TIMER_PERIOD Tmr_Per;
|
|
|
|
assert(WATCHDOG_TIMER != NULL);
|
|
|
|
switch(timer)
|
|
{
|
|
case MCAL_WDT_1_SEC_TIMER:
|
|
Clk_Div = DL_WWDT_CLOCK_DIVIDE_1;
|
|
Tmr_Per = DL_WWDT_TIMER_PERIOD_15_BITS;
|
|
break;
|
|
case MCAL_WDT_2_SEC_TIMER:
|
|
Clk_Div = DL_WWDT_CLOCK_DIVIDE_2;
|
|
Tmr_Per = DL_WWDT_TIMER_PERIOD_15_BITS;
|
|
break;
|
|
case MCAL_WDT_3_SEC_TIMER:
|
|
Clk_Div = DL_WWDT_CLOCK_DIVIDE_3;
|
|
Tmr_Per = DL_WWDT_TIMER_PERIOD_15_BITS;
|
|
break;
|
|
case MCAL_WDT_4_SEC_TIMER:
|
|
Clk_Div = DL_WWDT_CLOCK_DIVIDE_4;
|
|
Tmr_Per = DL_WWDT_TIMER_PERIOD_15_BITS;
|
|
break;
|
|
case MCAL_WDT_5_SEC_TIMER:
|
|
Clk_Div = DL_WWDT_CLOCK_DIVIDE_5;
|
|
Tmr_Per = DL_WWDT_TIMER_PERIOD_15_BITS;
|
|
break;
|
|
case MCAL_WDT_6_SEC_TIMER:
|
|
Clk_Div = DL_WWDT_CLOCK_DIVIDE_6;
|
|
Tmr_Per = DL_WWDT_TIMER_PERIOD_15_BITS;
|
|
break;
|
|
case MCAL_WDT_7_SEC_TIMER:
|
|
Clk_Div = DL_WWDT_CLOCK_DIVIDE_7;
|
|
Tmr_Per = DL_WWDT_TIMER_PERIOD_15_BITS;
|
|
break;
|
|
case MCAL_WDT_8_SEC_TIMER:
|
|
Clk_Div = DL_WWDT_CLOCK_DIVIDE_8;
|
|
Tmr_Per = DL_WWDT_TIMER_PERIOD_15_BITS;
|
|
break;
|
|
case MCAL_WDT_16_SEC_TIMER:
|
|
Clk_Div = DL_WWDT_CLOCK_DIVIDE_2;
|
|
Tmr_Per = DL_WWDT_TIMER_PERIOD_18_BITS;
|
|
break;
|
|
case MCAL_WDT_24_SEC_TIMER:
|
|
Clk_Div = DL_WWDT_CLOCK_DIVIDE_3;
|
|
Tmr_Per = DL_WWDT_TIMER_PERIOD_18_BITS;
|
|
break;
|
|
case MCAL_WDT_32_SEC_TIMER:
|
|
Clk_Div = DL_WWDT_CLOCK_DIVIDE_4;
|
|
Tmr_Per = DL_WWDT_TIMER_PERIOD_18_BITS;
|
|
break;
|
|
case MCAL_WDT_40_SEC_TIMER:
|
|
Clk_Div = DL_WWDT_CLOCK_DIVIDE_5;
|
|
Tmr_Per = DL_WWDT_TIMER_PERIOD_18_BITS;
|
|
break;
|
|
case MCAL_WDT_48_SEC_TIMER:
|
|
Clk_Div = DL_WWDT_CLOCK_DIVIDE_6;
|
|
Tmr_Per = DL_WWDT_TIMER_PERIOD_18_BITS;
|
|
break;
|
|
case MCAL_WDT_56_SEC_TIMER:
|
|
Clk_Div = DL_WWDT_CLOCK_DIVIDE_7;
|
|
Tmr_Per = DL_WWDT_TIMER_PERIOD_18_BITS;
|
|
break;
|
|
case MCAL_WDT_64_SEC_TIMER:
|
|
Clk_Div = DL_WWDT_CLOCK_DIVIDE_8;
|
|
Tmr_Per = DL_WWDT_TIMER_PERIOD_18_BITS;
|
|
break;
|
|
default: return IVEC_MCAL_STATUS_INIT_FAIL;
|
|
}
|
|
if(b_WDInitFlag == false)
|
|
{
|
|
/* Set Window0 as active window */
|
|
DL_WWDT_setActiveWindow(WATCHDOG_TIMER, DL_WWDT_WINDOW0);
|
|
|
|
DL_WWDT_initWatchdogMode(WATCHDOG_TIMER, Clk_Div,Tmr_Per, DL_WWDT_RUN_IN_SLEEP, DL_WWDT_WINDOW_PERIOD_0, DL_WWDT_WINDOW_PERIOD_0); // DL_WWDT_WINDOW_PERIOD_0 is for selecting the closed percentage of the watchdog
|
|
if(DL_WWDT_isPowerEnabled(WATCHDOG_TIMER))
|
|
{
|
|
while ((DL_SYSCTL_getClockStatus() & (DL_SYSCTL_CLK_STATUS_LFOSC_GOOD))!= (DL_SYSCTL_CLK_STATUS_LFOSC_GOOD));
|
|
}
|
|
else
|
|
{
|
|
|
|
return IVEC_MCAL_STATUS_TIMEOUT;
|
|
}
|
|
b_WDInitFlag = true;
|
|
|
|
return IVEC_MCAL_STATUS_SUCCESS;
|
|
}
|
|
else
|
|
{
|
|
return IVEC_MCAL_STATUS_INIT_FAIL;
|
|
}
|
|
}
|
|
|
|
IVEC_McalStatus_e xMCAL_WatchdogDeInit(void)
|
|
{
|
|
assert(WATCHDOG_TIMER != NULL);
|
|
|
|
if(b_WDInitFlag == true)
|
|
{
|
|
DL_WWDT_disablePower(WATCHDOG_TIMER);
|
|
|
|
b_WDInitFlag = false;
|
|
|
|
return IVEC_MCAL_STATUS_SUCCESS;
|
|
}
|
|
else
|
|
{
|
|
return IVEC_MCAL_STATUS_INIT_FAIL;
|
|
}
|
|
}
|
|
|
|
|
|
IVEC_McalStatus_e xMCAL_WatchdogReset(void)
|
|
{
|
|
if(DL_WWDT_isRunning(WATCHDOG_TIMER) == true)
|
|
{
|
|
DL_WWDT_restart(WATCHDOG_TIMER);
|
|
|
|
return IVEC_MCAL_STATUS_SUCCESS;
|
|
}
|
|
else
|
|
{
|
|
return IVEC_MCAL_STATUS_ERROR;
|
|
}
|
|
}
|