518 lines
17 KiB
C
518 lines
17 KiB
C
/*
|
|
* Copyright (c) 2023, Texas Instruments Incorporated
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions
|
|
* are met:
|
|
*
|
|
* * Redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer.
|
|
*
|
|
* * Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution.
|
|
*
|
|
* * Neither the name of Texas Instruments Incorporated nor the names of
|
|
* its contributors may be used to endorse or promote products derived
|
|
* from this software without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
|
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
|
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
|
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
|
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
|
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
|
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
|
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
|
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*/
|
|
|
|
/*
|
|
* ============ ti_msp_dl_config.c =============
|
|
* Configured MSPM0 DriverLib module definitions
|
|
*
|
|
* DO NOT EDIT - This file is generated for the MSPM0G350X
|
|
* by the SysConfig tool.
|
|
*/
|
|
///* Port definition for Pin Group GPIO_tick */
|
|
//#define GPIO_tick_PORT (GPIOA)
|
|
//
|
|
///* Defines for PIN_0: GPIOA.2 with pinCMx 7 on package pin 8 */
|
|
//#define tick_PIN_0_PIN (0x00004000)
|
|
|
|
#include "ti_msp_dl_config.h"
|
|
#include "../../utils/utils.h"
|
|
|
|
DL_TimerA_backupConfig gCAPTURE_0Backup;
|
|
DL_TimerA_backupConfig gTIMER_1Backup;
|
|
DL_MCAN_backupConfig gMCAN0Backup;
|
|
|
|
/*
|
|
* ======== SYSCFG_DL_init ========
|
|
* Perform any initialization needed before using any board APIs
|
|
*/
|
|
SYSCONFIG_WEAK void SYSCFG_DL_init(void)
|
|
{
|
|
SYSCFG_DL_initPower();
|
|
SYSCFG_DL_GPIO_init();
|
|
/* Module-Specific Initializations*/
|
|
SYSCFG_DL_SYSCTL_init();
|
|
SYSCFG_DL_CAPTURE_0_init();
|
|
SYSCFG_DL_TIMER_0_init();
|
|
SYSCFG_DL_TIMER_1_init();
|
|
//SYSCFG_DL_UART_0_init();
|
|
SYSCFG_DL_MCAN0_init();
|
|
SYSCFG_DL_SYSCTL_CLK_init();
|
|
/* Ensure backup structures have no valid state */
|
|
gCAPTURE_0Backup.backupRdy = false;
|
|
gTIMER_1Backup.backupRdy = false;
|
|
|
|
gMCAN0Backup.backupRdy = false;
|
|
|
|
}
|
|
/*
|
|
* User should take care to save and restore register configuration in application.
|
|
* See Retention Configuration section for more details.
|
|
*/
|
|
SYSCONFIG_WEAK bool SYSCFG_DL_saveConfiguration(void)
|
|
{
|
|
bool retStatus = true;
|
|
|
|
retStatus &= DL_TimerA_saveConfiguration(CAPTURE_0_INST, &gCAPTURE_0Backup);
|
|
retStatus &= DL_TimerA_saveConfiguration(TIMER_1_INST, &gTIMER_1Backup);
|
|
retStatus &= DL_MCAN_saveConfiguration(MCAN0_INST, &gMCAN0Backup);
|
|
|
|
return retStatus;
|
|
}
|
|
|
|
|
|
SYSCONFIG_WEAK bool SYSCFG_DL_restoreConfiguration(void)
|
|
{
|
|
bool retStatus = true;
|
|
|
|
retStatus &= DL_TimerA_restoreConfiguration(CAPTURE_0_INST, &gCAPTURE_0Backup, false);
|
|
retStatus &= DL_TimerA_restoreConfiguration(TIMER_1_INST, &gTIMER_1Backup, false);
|
|
retStatus &= DL_MCAN_restoreConfiguration(MCAN0_INST, &gMCAN0Backup);
|
|
|
|
return retStatus;
|
|
}
|
|
|
|
SYSCONFIG_WEAK void SYSCFG_DL_initPower(void)
|
|
{
|
|
DL_GPIO_reset(GPIOA);
|
|
DL_GPIO_reset(GPIOB);
|
|
DL_TimerA_reset(CAPTURE_0_INST);
|
|
DL_TimerG_reset(TIMER_0_INST);
|
|
DL_TimerA_reset(TIMER_1_INST);
|
|
|
|
DL_MCAN_reset(MCAN0_INST);
|
|
|
|
|
|
DL_GPIO_enablePower(GPIOA);
|
|
DL_GPIO_enablePower(GPIOB);
|
|
// #if UART_PIN_SELECTION == 1
|
|
// DL_UART_Main_reset(UART2);
|
|
// DL_UART_Main_enablePower(UART2);
|
|
//
|
|
// #elif UART_PIN_SELECTION == 2
|
|
// DL_UART_Main_reset(UART1);
|
|
// DL_UART_Main_enablePower(UART1);
|
|
//
|
|
// #elif UART_PIN_SELECTION == 3
|
|
// DL_UART_Main_reset(UART1);
|
|
// DL_UART_Main_enablePower(UART1);
|
|
// DL_UART_Main_reset(UART2);
|
|
// DL_UART_Main_enablePower(UART2);
|
|
//
|
|
// #endif
|
|
|
|
// DL_GPIO_enablePower(GPIOA);
|
|
// DL_GPIO_enablePower(GPIOB);
|
|
DL_TimerA_enablePower(CAPTURE_0_INST);
|
|
DL_TimerG_enablePower(TIMER_0_INST);
|
|
DL_TimerA_enablePower(TIMER_1_INST);
|
|
|
|
DL_MCAN_enablePower(MCAN0_INST);
|
|
delay_cycles(POWER_STARTUP_DELAY);
|
|
}
|
|
|
|
SYSCONFIG_WEAK void SYSCFG_DL_GPIO_init(void)
|
|
{
|
|
|
|
DL_GPIO_initPeripheralAnalogFunction(GPIO_HFXIN_IOMUX);
|
|
DL_GPIO_initPeripheralAnalogFunction(GPIO_HFXOUT_IOMUX);
|
|
|
|
DL_GPIO_initPeripheralInputFunction(GPIO_CAPTURE_0_C0_IOMUX, GPIO_CAPTURE_0_C0_IOMUX_FUNC);
|
|
|
|
DL_GPIO_initPeripheralOutputFunction(
|
|
GPIO_UART_0_IOMUX_TX, GPIO_UART_0_IOMUX_TX_FUNC);
|
|
DL_GPIO_initPeripheralInputFunction(
|
|
GPIO_UART_0_IOMUX_RX, GPIO_UART_0_IOMUX_RX_FUNC);
|
|
|
|
DL_GPIO_initDigitalInputFeatures(GPIO_GRP_0_PIN_0_IOMUX,
|
|
DL_GPIO_INVERSION_DISABLE, DL_GPIO_RESISTOR_NONE,
|
|
DL_GPIO_HYSTERESIS_DISABLE, DL_GPIO_WAKEUP_DISABLE);
|
|
// DL_GPIO_initDigitalOutput(GPIO_GRP_0_PIN_0_IOMUX);
|
|
|
|
DL_GPIO_initPeripheralOutputFunction(
|
|
GPIO_MCAN0_IOMUX_CAN_TX, GPIO_MCAN0_IOMUX_CAN_TX_FUNC);
|
|
DL_GPIO_initPeripheralInputFunction(
|
|
GPIO_MCAN0_IOMUX_CAN_RX, GPIO_MCAN0_IOMUX_CAN_RX_FUNC);
|
|
|
|
DL_GPIO_initDigitalInput(GPIO_GRP_0_soc_IOMUX);
|
|
|
|
|
|
// DL_GPIO_initDigitalInputFeatures(GPIO_GRP_0_soc_IOMUX,
|
|
// DL_GPIO_INVERSION_DISABLE, DL_GPIO_RESISTOR_PULL_DOWN,
|
|
// DL_GPIO_INVERSION_DISABLE, DL_GPIO_WAKEUP_DISABLE);
|
|
|
|
// DL_GPIO_initDigitalOutput(IOMUX_PINCM31);
|
|
//
|
|
// DL_GPIO_clearPins(GPIOB, tick_PIN_0_PIN);
|
|
// DL_GPIO_enableOutput(GPIOB, tick_PIN_0_PIN);
|
|
|
|
}
|
|
|
|
|
|
static const DL_SYSCTL_SYSPLLConfig gSYSPLLConfig = {
|
|
.inputFreq = DL_SYSCTL_SYSPLL_INPUT_FREQ_16_32_MHZ,
|
|
.rDivClk2x = 1,
|
|
.rDivClk1 = 0,
|
|
.rDivClk0 = 0,
|
|
.enableCLK2x = DL_SYSCTL_SYSPLL_CLK2X_DISABLE,
|
|
.enableCLK1 = DL_SYSCTL_SYSPLL_CLK1_DISABLE,
|
|
.enableCLK0 = DL_SYSCTL_SYSPLL_CLK0_ENABLE,
|
|
.sysPLLMCLK = DL_SYSCTL_SYSPLL_MCLK_CLK0,
|
|
.sysPLLRef = DL_SYSCTL_SYSPLL_REF_HFCLK,
|
|
.qDiv = 1,
|
|
.pDiv = DL_SYSCTL_SYSPLL_PDIV_1
|
|
};
|
|
SYSCONFIG_WEAK void SYSCFG_DL_SYSCTL_init(void)
|
|
{
|
|
|
|
//Low Power Mode is configured to be SLEEP0
|
|
DL_SYSCTL_setBORThreshold(DL_SYSCTL_BOR_THRESHOLD_LEVEL_0);
|
|
DL_SYSCTL_setFlashWaitState(DL_SYSCTL_FLASH_WAIT_STATE_2);
|
|
|
|
|
|
DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
|
|
/* Set default configuration */
|
|
DL_SYSCTL_disableHFXT();
|
|
DL_SYSCTL_disableSYSPLL();
|
|
DL_SYSCTL_setHFCLKSourceHFXTParams(DL_SYSCTL_HFXT_RANGE_16_32_MHZ,10, true);
|
|
DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *) &gSYSPLLConfig);
|
|
DL_SYSCTL_setULPCLKDivider(DL_SYSCTL_ULPCLK_DIV_1);
|
|
DL_SYSCTL_setMCLKSource(SYSOSC, HSCLK, DL_SYSCTL_HSCLK_SOURCE_SYSPLL);
|
|
|
|
}
|
|
SYSCONFIG_WEAK void SYSCFG_DL_SYSCTL_CLK_init(void) {
|
|
while ((DL_SYSCTL_getClockStatus() & (DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD
|
|
| DL_SYSCTL_CLK_STATUS_HFCLK_GOOD
|
|
| DL_SYSCTL_CLK_STATUS_HSCLK_GOOD
|
|
| DL_SYSCTL_CLK_STATUS_LFOSC_GOOD))
|
|
!= (DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD
|
|
| DL_SYSCTL_CLK_STATUS_HFCLK_GOOD
|
|
| DL_SYSCTL_CLK_STATUS_HSCLK_GOOD
|
|
| DL_SYSCTL_CLK_STATUS_LFOSC_GOOD))
|
|
{
|
|
/* Ensure that clocks are in default POR configuration before initialization.
|
|
* Additionally once LFXT is enabled, the internal LFOSC is disabled, and cannot
|
|
* be re-enabled other than by executing a BOOTRST. */
|
|
;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
* Timer clock configuration to be sourced by BUSCLK / (24000000 Hz)
|
|
* timerClkFreq = (timerClkSrc / (timerClkDivRatio * (timerClkPrescale + 1)))
|
|
* 12000000 Hz = 24000000 Hz / (1 * (1 + 1))
|
|
*/
|
|
static const DL_TimerA_ClockConfig gCAPTURE_0ClockConfig = {
|
|
.clockSel = DL_TIMER_CLOCK_BUSCLK,
|
|
.divideRatio = DL_TIMER_CLOCK_DIVIDE_1,
|
|
.prescale = 1U
|
|
};
|
|
|
|
/*
|
|
* Timer load value (where the counter starts from) is calculated as (timerPeriod * timerClockFreq) - 1
|
|
* CAPTURE_0_INST_LOAD_VALUE = (0 ms * 12000000 Hz) - 1
|
|
*/
|
|
static const DL_TimerA_CaptureConfig gCAPTURE_0CaptureConfig = {
|
|
.captureMode = DL_TIMER_CAPTURE_MODE_EDGE_TIME,
|
|
.period = CAPTURE_0_INST_LOAD_VALUE,
|
|
.startTimer = DL_TIMER_STOP,
|
|
.edgeCaptMode = DL_TIMER_CAPTURE_EDGE_DETECTION_MODE_RISING,
|
|
.inputChan = DL_TIMER_INPUT_CHAN_0,
|
|
.inputInvMode = DL_TIMER_CC_INPUT_INV_NOINVERT,
|
|
};
|
|
|
|
SYSCONFIG_WEAK void SYSCFG_DL_CAPTURE_0_init(void) {
|
|
|
|
DL_TimerA_setClockConfig(CAPTURE_0_INST,
|
|
(DL_TimerA_ClockConfig *) &gCAPTURE_0ClockConfig);
|
|
|
|
DL_TimerA_initCaptureMode(CAPTURE_0_INST,
|
|
(DL_TimerA_CaptureConfig *) &gCAPTURE_0CaptureConfig);
|
|
DL_TimerA_enableClock(CAPTURE_0_INST);
|
|
|
|
}
|
|
|
|
|
|
/*
|
|
* Timer clock configuration to be sourced by LFCLK / (32768 Hz)
|
|
* timerClkFreq = (timerClkSrc / (timerClkDivRatio * (timerClkPrescale + 1)))
|
|
* 992.969696969697 Hz = 32768 Hz / (1 * (32 + 1))
|
|
*/
|
|
static const DL_TimerG_ClockConfig gTIMER_0ClockConfig = {
|
|
.clockSel = DL_TIMER_CLOCK_LFCLK,
|
|
.divideRatio = DL_TIMER_CLOCK_DIVIDE_1,
|
|
.prescale = 32U,
|
|
};
|
|
|
|
/*
|
|
* Timer load value (where the counter starts from) is calculated as (timerPeriod * timerClockFreq) - 1
|
|
* TIMER_0_INST_LOAD_VALUE = (500 ms * 992.969696969697 Hz) - 1
|
|
*/
|
|
static const DL_TimerG_TimerConfig gTIMER_0TimerConfig = {
|
|
.period = TIMER_0_INST_LOAD_VALUE,
|
|
.timerMode = DL_TIMER_TIMER_MODE_PERIODIC,
|
|
.startTimer = DL_TIMER_STOP,
|
|
};
|
|
|
|
SYSCONFIG_WEAK void SYSCFG_DL_TIMER_0_init(void) {
|
|
|
|
DL_TimerG_setClockConfig(TIMER_0_INST,
|
|
(DL_TimerG_ClockConfig *) &gTIMER_0ClockConfig);
|
|
|
|
DL_TimerG_initTimerMode(TIMER_0_INST,
|
|
(DL_TimerG_TimerConfig *) &gTIMER_0TimerConfig);
|
|
DL_TimerG_enableInterrupt(TIMER_0_INST , DL_TIMERG_INTERRUPT_ZERO_EVENT);
|
|
DL_TimerG_enableClock(TIMER_0_INST);
|
|
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
/*
|
|
* Timer clock configuration to be sourced by LFCLK / (10922.666666666666 Hz)
|
|
* timerClkFreq = (timerClkSrc / (timerClkDivRatio * (timerClkPrescale + 1)))
|
|
* 10922.666666666666 Hz = 10922.666666666666 Hz / (3 * (0 + 1))
|
|
*/
|
|
static const DL_TimerA_ClockConfig gTIMER_1ClockConfig = {
|
|
.clockSel = DL_TIMER_CLOCK_LFCLK,
|
|
.divideRatio = DL_TIMER_CLOCK_DIVIDE_3,
|
|
.prescale = 0U,
|
|
};
|
|
|
|
/*
|
|
* Timer load value (where the counter starts from) is calculated as (timerPeriod * timerClockFreq) - 1
|
|
* TIMER_1_INST_LOAD_VALUE = (100 ms * 10922.666666666666 Hz) - 1
|
|
*/
|
|
static const DL_TimerA_TimerConfig gTIMER_1TimerConfig = {
|
|
.period = TIMER_1_INST_LOAD_VALUE,
|
|
.timerMode = DL_TIMER_TIMER_MODE_PERIODIC,
|
|
.startTimer = DL_TIMER_STOP,
|
|
};
|
|
|
|
SYSCONFIG_WEAK void SYSCFG_DL_TIMER_1_init(void) {
|
|
|
|
DL_TimerA_setClockConfig(TIMER_1_INST,
|
|
(DL_TimerA_ClockConfig *) &gTIMER_1ClockConfig);
|
|
|
|
DL_TimerA_initTimerMode(TIMER_1_INST,
|
|
(DL_TimerA_TimerConfig *) &gTIMER_1TimerConfig);
|
|
DL_TimerA_enableInterrupt(TIMER_1_INST , DL_TIMERA_INTERRUPT_ZERO_EVENT);
|
|
NVIC_SetPriority(TIMER_1_INST_INT_IRQN, 1);
|
|
DL_TimerA_enableClock(TIMER_1_INST);
|
|
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
static const DL_UART_Main_ClockConfig gUART_0ClockConfig = {
|
|
.clockSel = DL_UART_MAIN_CLOCK_BUSCLK,
|
|
.divideRatio = DL_UART_MAIN_CLOCK_DIVIDE_RATIO_1
|
|
};
|
|
|
|
static const DL_UART_Main_Config gUART_0Config = {
|
|
.mode = DL_UART_MAIN_MODE_NORMAL,
|
|
.direction = DL_UART_MAIN_DIRECTION_TX_RX,
|
|
.flowControl = DL_UART_MAIN_FLOW_CONTROL_NONE,
|
|
.parity = DL_UART_MAIN_PARITY_NONE,
|
|
.wordLength = DL_UART_MAIN_WORD_LENGTH_8_BITS,
|
|
.stopBits = DL_UART_MAIN_STOP_BITS_ONE
|
|
};
|
|
|
|
//SYSCONFIG_WEAK void SYSCFG_DL_UART_0_init(void)
|
|
//{
|
|
// DL_UART_Main_setClockConfig(UART_0_INST, (DL_UART_Main_ClockConfig *) &gUART_0ClockConfig);
|
|
//
|
|
// DL_UART_Main_init(UART_0_INST, (DL_UART_Main_Config *) &gUART_0Config);
|
|
// /*
|
|
// * Configure baud rate by setting oversampling and baud rate divisors.
|
|
// * Target baud rate: 115200
|
|
// * Actual baud rate: 115246.1
|
|
// */
|
|
// DL_UART_Main_setOversampling(UART_0_INST, DL_UART_OVERSAMPLING_RATE_16X);
|
|
// DL_UART_Main_setBaudRateDivisor(UART_0_INST, UART_0_IBRD_24_MHZ_115200_BAUD, UART_0_FBRD_24_MHZ_115200_BAUD);
|
|
//
|
|
//
|
|
//
|
|
// DL_UART_Main_enable(UART_0_INST);
|
|
//}
|
|
|
|
static const DL_MCAN_ClockConfig gMCAN0ClockConf = {
|
|
.clockSel = DL_MCAN_FCLK_HFCLK,
|
|
.divider = DL_MCAN_FCLK_DIV_1,
|
|
};
|
|
|
|
static const DL_MCAN_InitParams gMCAN0InitParams= {
|
|
|
|
/* Initialize MCAN Init parameters. */
|
|
.fdMode = false,
|
|
.brsEnable = false,
|
|
.txpEnable = false,
|
|
.efbi = false,
|
|
.pxhddisable = false,
|
|
.darEnable = false,
|
|
.wkupReqEnable = false,
|
|
.autoWkupEnable = false,
|
|
.emulationEnable = false,
|
|
.tdcEnable = false,
|
|
.wdcPreload = 255,
|
|
|
|
/* Transmitter Delay Compensation parameters. */
|
|
.tdcConfig.tdcf = 10,
|
|
.tdcConfig.tdco = 6,
|
|
};
|
|
|
|
|
|
static const DL_MCAN_MsgRAMConfigParams gMCAN0MsgRAMConfigParams ={
|
|
|
|
/* Standard ID Filter List Start Address. */
|
|
.flssa = MCAN0_INST_MCAN_STD_ID_FILT_START_ADDR,
|
|
/* List Size: Standard ID. */
|
|
.lss = MCAN0_INST_MCAN_STD_ID_FILTER_NUM,
|
|
/* Extended ID Filter List Start Address. */
|
|
.flesa = MCAN0_INST_MCAN_EXT_ID_FILT_START_ADDR,
|
|
/* List Size: Extended ID. */
|
|
.lse = MCAN0_INST_MCAN_EXT_ID_FILTER_NUM,
|
|
/* Tx Buffers Start Address. */
|
|
.txStartAddr = MCAN0_INST_MCAN_TX_BUFF_START_ADDR,
|
|
/* Number of Dedicated Transmit Buffers. */
|
|
.txBufNum = MCAN0_INST_MCAN_TX_BUFF_SIZE,
|
|
.txFIFOSize = 0,
|
|
/* Tx Buffer Element Size. */
|
|
.txBufMode = 0,
|
|
.txBufElemSize = DL_MCAN_ELEM_SIZE_64BYTES,
|
|
/* Tx Event FIFO Start Address. */
|
|
.txEventFIFOStartAddr = MCAN0_INST_MCAN_TX_EVENT_START_ADDR,
|
|
/* Event FIFO Size. */
|
|
.txEventFIFOSize = MCAN0_INST_MCAN_TX_EVENT_SIZE,
|
|
/* Level for Tx Event FIFO watermark interrupt. */
|
|
.txEventFIFOWaterMark = 3,
|
|
/* Rx FIFO0 Start Address. */
|
|
.rxFIFO0startAddr = MCAN0_INST_MCAN_FIFO_0_START_ADDR,
|
|
/* Number of Rx FIFO elements. */
|
|
.rxFIFO0size = MCAN0_INST_MCAN_FIFO_0_NUM,
|
|
/* Rx FIFO0 Watermark. */
|
|
.rxFIFO0waterMark = 3,
|
|
.rxFIFO0OpMode = 0,
|
|
/* Rx FIFO1 Start Address. */
|
|
.rxFIFO1startAddr = MCAN0_INST_MCAN_FIFO_1_START_ADDR,
|
|
/* Number of Rx FIFO elements. */
|
|
.rxFIFO1size = MCAN0_INST_MCAN_FIFO_1_NUM,
|
|
/* Level for Rx FIFO 1 watermark interrupt. */
|
|
.rxFIFO1waterMark = 3,
|
|
/* FIFO blocking mode. */
|
|
.rxFIFO1OpMode = 0,
|
|
/* Rx Buffer Start Address. */
|
|
.rxBufStartAddr = MCAN0_INST_MCAN_RX_BUFF_START_ADDR,
|
|
/* Rx Buffer Element Size. */
|
|
.rxBufElemSize = DL_MCAN_ELEM_SIZE_64BYTES,
|
|
/* Rx FIFO0 Element Size. */
|
|
.rxFIFO0ElemSize = DL_MCAN_ELEM_SIZE_64BYTES,
|
|
/* Rx FIFO1 Element Size. */
|
|
.rxFIFO1ElemSize = DL_MCAN_ELEM_SIZE_64BYTES,
|
|
};
|
|
|
|
|
|
|
|
static const DL_MCAN_BitTimingParams gMCAN0BitTimes = {
|
|
/* Arbitration Baud Rate Pre-scaler. */
|
|
.nomRatePrescalar = 0,
|
|
/* Arbitration Time segment before sample point. */
|
|
.nomTimeSeg1 = 40,
|
|
/* Arbitration Time segment after sample point. */
|
|
.nomTimeSeg2 = 5,
|
|
/* Arbitration (Re)Synchronization Jump Width Range. */
|
|
.nomSynchJumpWidth = 5,
|
|
/* Data Baud Rate Pre-scaler. */
|
|
.dataRatePrescalar = 0,
|
|
/* Data Time segment before sample point. */
|
|
.dataTimeSeg1 = 0,
|
|
/* Data Time segment after sample point. */
|
|
.dataTimeSeg2 = 0,
|
|
/* Data (Re)Synchronization Jump Width. */
|
|
.dataSynchJumpWidth = 0,
|
|
};
|
|
|
|
|
|
SYSCONFIG_WEAK void SYSCFG_DL_MCAN0_init(void) {
|
|
DL_MCAN_RevisionId revid_MCAN0;
|
|
|
|
DL_MCAN_enableModuleClock(MCAN0_INST);
|
|
|
|
DL_MCAN_setClockConfig(MCAN0_INST, (DL_MCAN_ClockConfig *) &gMCAN0ClockConf);
|
|
|
|
/* Get MCANSS Revision ID. */
|
|
DL_MCAN_getRevisionId(MCAN0_INST, &revid_MCAN0);
|
|
|
|
/* Wait for Memory initialization to be completed. */
|
|
while(false == DL_MCAN_isMemInitDone(MCAN0_INST));
|
|
|
|
/* Put MCAN in SW initialization mode. */
|
|
|
|
DL_MCAN_setOpMode(MCAN0_INST, DL_MCAN_OPERATION_MODE_SW_INIT);
|
|
|
|
/* Wait till MCAN is not initialized. */
|
|
while (DL_MCAN_OPERATION_MODE_SW_INIT != DL_MCAN_getOpMode(MCAN0_INST));
|
|
|
|
/* Initialize MCAN module. */
|
|
DL_MCAN_init(MCAN0_INST, (DL_MCAN_InitParams *) &gMCAN0InitParams);
|
|
|
|
|
|
/* Configure Bit timings. */
|
|
DL_MCAN_setBitTime(MCAN0_INST, (DL_MCAN_BitTimingParams*) &gMCAN0BitTimes);
|
|
|
|
/* Configure Message RAM Sections */
|
|
DL_MCAN_msgRAMConfig(MCAN0_INST, (DL_MCAN_MsgRAMConfigParams*) &gMCAN0MsgRAMConfigParams);
|
|
|
|
|
|
|
|
/* Set Extended ID Mask. */
|
|
DL_MCAN_setExtIDAndMask(MCAN0_INST, MCAN0_INST_MCAN_EXT_ID_AND_MASK );
|
|
|
|
/* Loopback mode */
|
|
|
|
/* Take MCAN out of the SW initialization mode */
|
|
DL_MCAN_setOpMode(MCAN0_INST, DL_MCAN_OPERATION_MODE_NORMAL);
|
|
|
|
while (DL_MCAN_OPERATION_MODE_NORMAL != DL_MCAN_getOpMode(MCAN0_INST));
|
|
|
|
|
|
}
|
|
|