151 lines
4.2 KiB
C
151 lines
4.2 KiB
C
/*utils.c
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* @Created on: 22-Jan-2024
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* @Author: Vecmocon Technology
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*/
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#include <utils/utils.h>
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#include "../Generated Codes/ti_msp_config.h"
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static volatile uint32_t g_vrefInitFlag = 0;
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volatile int g_i32TickCnt;
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uint8_t g_systickInitFlag_u8 = 0;
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static const DL_VREF_Config g_dlVrefConfig = {
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.vrefEnable = DL_VREF_ENABLE_DISABLE,
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.bufConfig = DL_VREF_BUFCONFIG_OUTPUT_2_5V,
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.shModeEnable = DL_VREF_SHMODE_DISABLE,
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.holdCycleCount = DL_VREF_HOLD_MIN,
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.shCycleCount = DL_VREF_SH_MIN,
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};
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static const DL_VREF_ClockConfig g_dlVrefClockConfig = {
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.clockSel = DL_VREF_CLOCK_LFCLK,
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.divideRatio = DL_VREF_CLOCK_DIVIDE_1,
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};
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/* Systick Initialization */
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IVEC_CoreStatus_e xMCAL_SystickInit(IVEC_SystickPeriod_e eTick)
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{
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SysTick_Config(eTick);
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NVIC_SetPriority(SysTick_IRQn, 0);
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g_systickInitFlag_u8 = 1;
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return IVEC_CORE_STATUS_SUCCESS;
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}
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static const DL_SYSCTL_SYSPLLConfig g_dlSysPllConfig = {
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.inputFreq = DL_SYSCTL_SYSPLL_INPUT_FREQ_16_32_MHZ,
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.rDivClk2x = 1,
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.rDivClk1 = 0,
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.rDivClk0 = 0,
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.enableCLK2x = DL_SYSCTL_SYSPLL_CLK2X_DISABLE,
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.enableCLK1 = DL_SYSCTL_SYSPLL_CLK1_DISABLE,
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.enableCLK0 = DL_SYSCTL_SYSPLL_CLK0_ENABLE,
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.sysPLLMCLK = DL_SYSCTL_SYSPLL_MCLK_CLK0,
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.sysPLLRef = DL_SYSCTL_SYSPLL_REF_HFCLK,
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.qDiv = 5,
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.pDiv = DL_SYSCTL_SYSPLL_PDIV_1,
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};
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/* System Control Initialization */
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IVEC_CoreStatus_e xMCAL_SysctlInit(uint8_t u8ClkSrc, uint8_t u8LowPowerMode)
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{
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if ((u8LowPowerMode != IVEC_STANDBY0) && (u8LowPowerMode != IVEC_SLEEP0))
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return IVEC_CORE_STATUS_INIT_FAIL;
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if ((u8ClkSrc != IVEC_HFXT) && (u8ClkSrc != IVEC_SYSOSC))
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return IVEC_CORE_STATUS_INIT_FAIL;
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if (u8LowPowerMode == IVEC_STANDBY0)
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{
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DL_SYSCTL_setPowerPolicySTANDBY0();
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DL_SYSCTL_setBORThreshold(DL_SYSCTL_BOR_THRESHOLD_LEVEL_0);
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DL_SYSCTL_setFlashWaitState(DL_SYSCTL_FLASH_WAIT_STATE_2);
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}
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else if (u8LowPowerMode == IVEC_SLEEP0)
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{
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DL_SYSCTL_setBORThreshold(DL_SYSCTL_BOR_THRESHOLD_LEVEL_0);
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DL_SYSCTL_setFlashWaitState(DL_SYSCTL_FLASH_WAIT_STATE_2);
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}
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if (u8ClkSrc == IVEC_HFXT)
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{
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DL_SYSCTL_setBORThreshold(DL_SYSCTL_BOR_THRESHOLD_LEVEL_0);
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DL_SYSCTL_setFlashWaitState(DL_SYSCTL_FLASH_WAIT_STATE_2);
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DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
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DL_SYSCTL_disableHFXT();
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DL_SYSCTL_disableSYSPLL();
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DL_SYSCTL_setHFCLKSourceHFXTParams(DL_SYSCTL_HFXT_RANGE_16_32_MHZ, 10, true);
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DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *)&g_dlSysPllConfig);
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DL_SYSCTL_setULPCLKDivider(DL_SYSCTL_ULPCLK_DIV_2);
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DL_SYSCTL_setMCLKSource(SYSOSC, HSCLK, DL_SYSCTL_HSCLK_SOURCE_SYSPLL);
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}
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else if (u8ClkSrc == IVEC_SYSOSC)
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{
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DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
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DL_SYSCTL_disableHFXT();
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DL_SYSCTL_disableSYSPLL();
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DL_SYSCTL_setHFCLKSourceHFXTParams(DL_SYSCTL_HFXT_RANGE_16_32_MHZ, 50, true);
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DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *)&g_dlSysPllConfig);
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DL_SYSCTL_setHFCLKDividerForMFPCLK(DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_6);
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DL_SYSCTL_enableMFCLK();
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DL_SYSCTL_enableMFPCLK();
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DL_SYSCTL_setMFPCLKSource(DL_SYSCTL_MFPCLK_SOURCE_SYSOSC);
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}
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return IVEC_CORE_STATUS_SUCCESS;
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}
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void SysTick_Handler(void)
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{
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g_i32TickCnt++;
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}
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int32_t i32MCAL_GetTicks()
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{
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return g_i32TickCnt;
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}
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void vMCAL_DelayTicks(int32_t i32DelayMs)
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{
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int32_t l_i32CurrTick = i32MCAL_GetTicks();
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while ((i32MCAL_GetTicks() - l_i32CurrTick) < i32DelayMs)
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{
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/* Wait */
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}
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}
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void vMCAL_McuInit(void)
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{
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SYSCFG_DL_initPower();
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SYSCFG_DL_GPIO_init();
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}
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void vMCAL_DelayUs(uint32_t u32Us)
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{
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delay_cycles(32 * u32Us);
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}
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IVEC_McalStatus_e xMCAL_VrefInit(void)
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{
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if (g_vrefInitFlag == 0)
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{
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DL_VREF_setClockConfig(VREF, (DL_VREF_ClockConfig *)&g_dlVrefClockConfig);
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DL_VREF_configReference(VREF, (DL_VREF_Config *)&g_dlVrefConfig);
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delay_cycles(320);
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g_vrefInitFlag = 1;
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return IVEC_MCAL_STATUS_SUCCESS;
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}
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else
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{
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return IVEC_MCAL_STATUS_INIT_FAIL;
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}
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}
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void vMCAL_SoftReset(void)
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{
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DL_SYSCTL_resetDevice(DL_SYSCTL_RESET_CPU);
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}
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