266 lines
8.3 KiB
C
266 lines
8.3 KiB
C
/*utils.c
|
|
* @Created on: 22-Jan-2024
|
|
* @Author: Vecmocon Technology
|
|
*/
|
|
|
|
#include <utils/utils.h>
|
|
#include "../Generated Codes/ti_msp_config.h"
|
|
|
|
volatile uint32_t systic_Count;
|
|
volatile uint32_t systic_init_flag =0;
|
|
static volatile uint32_t g_u32VrefInitFalg = 0;
|
|
|
|
static const DL_VREF_Config gVREFConfig = {
|
|
.vrefEnable = DL_VREF_ENABLE_DISABLE,
|
|
.bufConfig = DL_VREF_BUFCONFIG_OUTPUT_2_5V,
|
|
.shModeEnable = DL_VREF_SHMODE_DISABLE,
|
|
.holdCycleCount = DL_VREF_HOLD_MIN,
|
|
.shCycleCount = DL_VREF_SH_MIN,
|
|
};
|
|
|
|
static const DL_VREF_ClockConfig gVREFClockConfig = {
|
|
.clockSel = DL_VREF_CLOCK_LFCLK,
|
|
.divideRatio = DL_VREF_CLOCK_DIVIDE_1,
|
|
};
|
|
|
|
|
|
uint8_t u8SysTick_initFlag=0;
|
|
|
|
//static const DL_SYSCTL_SYSPLLConfig gSYSPLLConfig = {
|
|
// .inputFreq = DL_SYSCTL_SYSPLL_INPUT_FREQ_16_32_MHZ,
|
|
// .rDivClk2x = 1,
|
|
// .rDivClk1 = 1,
|
|
// .rDivClk0 = 0,
|
|
// .enableCLK2x = DL_SYSCTL_SYSPLL_CLK2X_DISABLE,
|
|
// .enableCLK1 = DL_SYSCTL_SYSPLL_CLK1_ENABLE,
|
|
// .enableCLK0 = DL_SYSCTL_SYSPLL_CLK0_DISABLE,
|
|
// .sysPLLMCLK = DL_SYSCTL_SYSPLL_MCLK_CLK0,
|
|
// .sysPLLRef = DL_SYSCTL_SYSPLL_REF_SYSOSC,
|
|
// .qDiv = 9,
|
|
// .pDiv = DL_SYSCTL_SYSPLL_PDIV_2
|
|
//};
|
|
|
|
static const DL_SYSCTL_SYSPLLConfig gSYSPLLConfig = {
|
|
.inputFreq = DL_SYSCTL_SYSPLL_INPUT_FREQ_8_16_MHZ,
|
|
.rDivClk2x = 1,
|
|
.rDivClk1 = 0,
|
|
.rDivClk0 = 0,
|
|
.enableCLK2x = DL_SYSCTL_SYSPLL_CLK2X_DISABLE,
|
|
.enableCLK1 = DL_SYSCTL_SYSPLL_CLK1_ENABLE,
|
|
.enableCLK0 = DL_SYSCTL_SYSPLL_CLK0_DISABLE,
|
|
.sysPLLMCLK = DL_SYSCTL_SYSPLL_MCLK_CLK0,
|
|
.sysPLLRef = DL_SYSCTL_SYSPLL_REF_SYSOSC,
|
|
.qDiv = 9,
|
|
.pDiv = DL_SYSCTL_SYSPLL_PDIV_4
|
|
};
|
|
void mcuInit(void)
|
|
{
|
|
SYSCFG_DL_initPower();
|
|
|
|
/* Module-Specific Initializations*/
|
|
}
|
|
|
|
xCoreStatus_t xMCAL_SYSTICK_INIT(xTicks_t tick)
|
|
{
|
|
if(u8SysTick_initFlag==1)
|
|
{
|
|
return STATUS_ERROR;
|
|
}
|
|
|
|
if(tick!=Period_1ms)
|
|
{
|
|
return STATUS_INIT_FAIL;
|
|
}
|
|
|
|
SysTick_Config(tick);
|
|
|
|
u8SysTick_initFlag=1;
|
|
|
|
return STATUS_SUCCESS;
|
|
|
|
}
|
|
|
|
xCoreStatus_t xMCAL_SYSCTL_INIT(uint8_t u8CLK_SRC,uint8_t u8LP_MODE)
|
|
{
|
|
if((u8LP_MODE!=STANDBY0)&&(u8LP_MODE!=SLEEP0))
|
|
return STATUS_INIT_FAIL;
|
|
if((u8CLK_SRC!=HFXT)&&(u8CLK_SRC!=SYSOSC))
|
|
return STATUS_INIT_FAIL;
|
|
|
|
if(u8LP_MODE==STANDBY0)
|
|
{
|
|
//Low Power Mode is configured to be STANDBY0
|
|
DL_SYSCTL_setPowerPolicySTANDBY0();
|
|
DL_SYSCTL_setBORThreshold(DL_SYSCTL_BOR_THRESHOLD_LEVEL_0);
|
|
DL_SYSCTL_setFlashWaitState(DL_SYSCTL_FLASH_WAIT_STATE_2);
|
|
}
|
|
else if(u8LP_MODE==SLEEP0)
|
|
{
|
|
DL_SYSCTL_setBORThreshold(DL_SYSCTL_BOR_THRESHOLD_LEVEL_0);
|
|
DL_SYSCTL_setFlashWaitState(DL_SYSCTL_FLASH_WAIT_STATE_2);
|
|
|
|
}
|
|
|
|
if(u8CLK_SRC==HFXT)
|
|
{
|
|
|
|
|
|
|
|
DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
|
|
/* Set default configuration */
|
|
DL_SYSCTL_disableHFXT();
|
|
DL_SYSCTL_disableSYSPLL();
|
|
DL_SYSCTL_setHFCLKSourceHFXTParams(DL_SYSCTL_HFXT_RANGE_16_32_MHZ,10, true);
|
|
DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *) &gSYSPLLConfig);
|
|
DL_SYSCTL_setULPCLKDivider(DL_SYSCTL_ULPCLK_DIV_1);
|
|
DL_SYSCTL_setHFCLKDividerForMFPCLK(DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_6);
|
|
DL_SYSCTL_enableMFCLK();
|
|
DL_SYSCTL_enableMFPCLK();
|
|
DL_SYSCTL_setMFPCLKSource(DL_SYSCTL_MFPCLK_SOURCE_HFCLK);
|
|
DL_SYSCTL_setMCLKSource(SYSOSC, HSCLK, DL_SYSCTL_HSCLK_SOURCE_HFCLK);
|
|
// DL_SYSCTL_setHFCLKSourceHFXTParams(DL_SYSCTL_HFXT_RANGE_16_32_MHZ,0, false);
|
|
// DL_SYSCTL_setULPCLKDivider(DL_SYSCTL_ULPCLK_DIV_1);
|
|
// DL_SYSCTL_setMCLKSource(SYSOSC, HSCLK, DL_SYSCTL_HSCLK_SOURCE_HFCLK);
|
|
|
|
|
|
//DL_SYSCTL_setHFCLKSourceHFXTParams(DL_SYSCTL_HFXT_RANGE_32_48_MHZ,0, false);
|
|
// DL_SYSCTL_setHFCLKSourceHFXTParams(DL_SYSCTL_HFXT_RANGE_16_32_MHZ,0, false);
|
|
// DL_SYSCTL_setULPCLKDivider(DL_SYSCTL_ULPCLK_DIV_1);
|
|
// DL_SYSCTL_setMCLKSource(SYSOSC, HSCLK, DL_SYSCTL_HSCLK_SOURCE_HFCLK);
|
|
}
|
|
|
|
else if(u8CLK_SRC==SYSOSC)
|
|
{
|
|
// DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
|
|
// /* Set default configuration */
|
|
// DL_SYSCTL_disableHFXT();
|
|
// DL_SYSCTL_disableSYSPLL();
|
|
// DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *) &gSYSPLLConfig);
|
|
DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
|
|
DL_SYSCTL_disableHFXT();
|
|
DL_SYSCTL_disableSYSPLL();
|
|
DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *) &gSYSPLLConfig);
|
|
DL_SYSCTL_setHFCLKDividerForMFPCLK(DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_6);
|
|
DL_SYSCTL_enableMFCLK();
|
|
DL_SYSCTL_enableMFPCLK();
|
|
DL_SYSCTL_setMFPCLKSource(DL_SYSCTL_MFPCLK_SOURCE_SYSOSC);
|
|
}
|
|
|
|
return STATUS_SUCCESS;
|
|
|
|
}
|
|
|
|
void SysTick_Handler(void)
|
|
{
|
|
i32TickCnt++;
|
|
|
|
}
|
|
|
|
int i32MCAL_getTicks()
|
|
{
|
|
return i32TickCnt;
|
|
}
|
|
|
|
void vMCAL_DelayTicks(int i32Delay_ms)
|
|
{
|
|
int curr_tick;
|
|
curr_tick=i32MCAL_getTicks();
|
|
|
|
while((i32MCAL_getTicks()-curr_tick)<i32Delay_ms);
|
|
|
|
return;
|
|
}
|
|
|
|
//void delay (uint32_t us)
|
|
//{
|
|
// delay_cycles((40*us));
|
|
//}
|
|
|
|
|
|
|
|
void xMCAL_McuInit()
|
|
{
|
|
// DL_initPower();
|
|
// DL_init();
|
|
// DL_SYSCTL_init();
|
|
// xMCAL_VrefInit();
|
|
SYSCFG_DL_initPower();
|
|
DL_UART_Main_reset(UART2);
|
|
DL_UART_Main_enablePower(UART2);
|
|
SYSCFG_DL_GPIO_init();
|
|
}
|
|
|
|
//void vMCAL_GPIO_init(void)
|
|
//{
|
|
//
|
|
// DL_GPIO_initPeripheralOutputFunction(GPIO_PWM_0_C0_IOMUX,GPIO_PWM_0_C0_IOMUX_FUNC);
|
|
// DL_GPIO_enableOutput(GPIO_PWM_0_C0_PORT, GPIO_PWM_0_C0_PIN);
|
|
//
|
|
// DL_GPIO_initPeripheralInputFunction(GPIO_CAPTURE_0_C0_IOMUX,GPIO_CAPTURE_0_C0_IOMUX_FUNC);
|
|
//
|
|
// DL_GPIO_initPeripheralInputFunctionFeatures(GPIO_I2C_0_IOMUX_SDA,
|
|
// GPIO_I2C_0_IOMUX_SDA_FUNC, DL_GPIO_INVERSION_DISABLE,
|
|
// DL_GPIO_RESISTOR_NONE, DL_GPIO_HYSTERESIS_DISABLE,
|
|
// DL_GPIO_WAKEUP_DISABLE);
|
|
// DL_GPIO_initPeripheralInputFunctionFeatures(GPIO_I2C_0_IOMUX_SCL,
|
|
// GPIO_I2C_0_IOMUX_SCL_FUNC, DL_GPIO_INVERSION_DISABLE,
|
|
// DL_GPIO_RESISTOR_NONE, DL_GPIO_HYSTERESIS_DISABLE,
|
|
// DL_GPIO_WAKEUP_DISABLE);
|
|
// DL_GPIO_enableHiZ(GPIO_I2C_0_IOMUX_SDA);
|
|
// DL_GPIO_enableHiZ(GPIO_I2C_0_IOMUX_SCL);
|
|
//
|
|
// DL_GPIO_initPeripheralOutputFunction(
|
|
// GPIO_UART_0_IOMUX_TX, GPIO_UART_0_IOMUX_TX_FUNC);
|
|
// DL_GPIO_initPeripheralInputFunction(
|
|
// GPIO_UART_0_IOMUX_RX, GPIO_UART_0_IOMUX_RX_FUNC);
|
|
// DL_GPIO_initPeripheralOutputFunction(
|
|
// GPIO_UART_1_IOMUX_TX, GPIO_UART_1_IOMUX_TX_FUNC);
|
|
// DL_GPIO_initPeripheralInputFunction(
|
|
// GPIO_UART_1_IOMUX_RX, GPIO_UART_1_IOMUX_RX_FUNC);
|
|
//
|
|
// DL_GPIO_initPeripheralOutputFunction(
|
|
// GPIO_SPI_0_IOMUX_SCLK, GPIO_SPI_0_IOMUX_SCLK_FUNC);
|
|
// DL_GPIO_initPeripheralOutputFunction(
|
|
// GPIO_SPI_0_IOMUX_PICO, GPIO_SPI_0_IOMUX_PICO_FUNC);
|
|
// DL_GPIO_initPeripheralInputFunction(
|
|
// GPIO_SPI_0_IOMUX_POCI, GPIO_SPI_0_IOMUX_POCI_FUNC);
|
|
//
|
|
// DL_GPIO_initDigitalOutput(GPIO_LCD_A_PIN_DB4_IOMUX);
|
|
//
|
|
// DL_GPIO_initDigitalOutput(GPIO_SPI_CS_SPI_CS_IOMUX);
|
|
//
|
|
// DL_GPIO_clearPins(GPIO_LCD_A_PORT, GPIO_LCD_A_PIN_DB4_PIN);
|
|
// DL_GPIO_enableOutput(GPIO_LCD_A_PORT, GPIO_LCD_A_PIN_DB4_PIN);
|
|
// DL_GPIO_setPins(GPIO_SPI_CS_PORT, GPIO_SPI_CS_SPI_CS_PIN);
|
|
// DL_GPIO_enableOutput(GPIO_SPI_CS_PORT, GPIO_SPI_CS_SPI_CS_PIN);
|
|
//
|
|
// DL_GPIO_initPeripheralOutputFunction(
|
|
// GPIO_MCAN0_IOMUX_CAN_TX, GPIO_MCAN0_IOMUX_CAN_TX_FUNC);
|
|
// DL_GPIO_initPeripheralInputFunction(
|
|
// GPIO_MCAN0_IOMUX_CAN_RX, GPIO_MCAN0_IOMUX_CAN_RX_FUNC);
|
|
//}
|
|
|
|
|
|
|
|
void delay(uint32_t us)
|
|
{
|
|
delay_cycles((32*us));
|
|
}
|
|
|
|
|
|
IVEC_McalStatus_e xMCAL_VrefInit(void)
|
|
{
|
|
if(g_u32VrefInitFalg == 0)
|
|
{
|
|
DL_VREF_setClockConfig(VREF, (DL_VREF_ClockConfig *) &gVREFClockConfig);
|
|
DL_VREF_configReference(VREF,(DL_VREF_Config *) &gVREFConfig);
|
|
delay_cycles(320);
|
|
g_u32VrefInitFalg =1;
|
|
return IVEC_MCAL_STATUS_SUCCESS;
|
|
}
|
|
else
|
|
return IVEC_MCAL_STATUS_INIT_FAIL;
|
|
}
|
|
|
|
|